Parallel data processing apparatus

• US 7,802,079 B2
• Filed: 06/29/2007
• Issued: 09/21/2010
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: ClearSpeed Technology Ltd. (ZF Acquisitions Ltd.)
• Inventors: McConnell, Ray, Rhoades, John, Cameron, Ken, Winser, Paul, Faulds, Gordon, David, Russell, Greer, Trey, Atkin, Phil, Stuttard, Dave, Day, Tim, Williams, Dave, O'Dea, Eamon
• Primary Examiner(s): Li; Aimee J
• Application Number:
  US11/772,079
• Publication Number:
  US 20080034186A1
• Time in Patent Office: 1,180 Days
• Field of Search: 712/14, 712/22, 712/216, 712/217, 712/225
• US Class Current: 712/225
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Claims

1. A register score-boarding unit for use in an array controller for controlling the operation of a SIMD (single instruction multiple data) array of processing elements in which the processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items, the array controller comprising a processing element instruction sequencer for handling data processing instructions and a data transfer controller for handling data transfer instructions, the register score-boarding unit comprising:

means for maintaining the appearance of serial instruction execution while achieving parallel operation between the processing element instruction sequencer and the data transfer controller;

an enable stack to determine whether a processing element is permitted to process data supplied to it; and

means to stall a load/store instruction, in response to an executing microcode-instruction that modifies the enable stack.

2. A unit as claimed in claim 1, provided on a single integrated circuit.

3. A graphical data processing system comprising a host general data processing apparatus and a register score-boarding unit as claimed in claim 1 for processing graphical data.