Thin-film transistor array, method of fabricating the same, and liquid crystal display device including the same

• US 7,804,091 B2
• Filed: 08/07/2007
• Issued: 09/28/2010
• Est. Priority Date: 08/09/2006
• Status: Active Grant

• Current Assignee: NLT Technologies, Ltd.
• Original Assignee: NEC Corporation, NEC LCD Technologies Limited (NEC Corporation)
• Inventors: Takechi, Kazushige, Nakata, Mitsuru
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US11/890,677
• Publication Number:
  US 20080035920A1
• Time in Patent Office: 1,148 Days
• Field of Search: 349/43, 349/46, 349/4, 349/462, 257/59, 257/72
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin-film transistor array includes an electrically insulating substrate, a plurality of thin-film transistors arranged in a matrix on the substrate, and each including a channel, a source, and a drain each comprised of an oxide-semiconductor film, a pixel electrode integrally formed with the drain, a source signal line through which a source signal is transmitted to a group of thin-film transistors, a gate signal line through which a gate signal is transmitted to a group of thin-film transistors, a source terminal formed at an end of the source signal line, and a gate terminal formed at an end of the gate signal line. The source terminal and the gate terminal are formed in the same layer as a layer in which the channel is formed. The source terminal and the gate terminal have the same electric conductivity as that of the pixel electrode.

Claims

1. A thin-film transistor array comprising:

an electrically insulating substrate;

a plurality of thin-film transistors arranged in a matrix on said electrically insulating substrate, and each including a channel, a source, and a drain each comprised of an oxide-semiconductor film;

a pixel electrode integrally formed with said drain;

a source signal line through which a source signal is transmitted to a group of thin-film transistors among said plurality of thin-film transistors;

a gate signal line through which a gate signal is transmitted to a group of thin-film transistors among said plurality of thin-film transistors;

a gate insulating layer formed above the gate signal line, the gate insulating layer having a gate terminal contact hole;

a source terminal formed at an end of said source signal line; and

a gate terminal formed in said gate terminal contact hole in contact with said gate signal line at an end of said gate signal line,

said source terminal and said gate terminal being formed in the same layer of oxide-semiconductor film as a layer in which said channel, drain and source are formed,

said source terminal and said gate terminal having the same electric conductivity as that of said pixel electrode.

2. The thin-film transistor array as set forth in claim 1, wherein said oxide-semiconductor film is composed of amorphous oxide containing at least one of Zn, Ga and In.

3. The thin-film transistor array as set forth in claim 1, wherein said oxide-semiconductor film is composed of crystalline oxide containing at least one of Zn, Ga and In.

4. The thin-film transistor array as set forth in claim 1, wherein said oxide-semiconductor film is composed of mixed crystal including both amorphous oxide containing at least one of Zn, Ga and In, and polycrystal oxide.

5. The thin-film transistor array as set forth in claim 1, wherein said oxide-semiconductor film is formed by dissolving powdered oxide semiconductor into solvent, coating or printing said solvent onto an object, and heating said solvent to vaporize said solvent.

6. The thin-film transistor array as set forth in claim 1, wherein said electrically insulating substrate is comprised of a resin substrate.

7. A liquid crystal display device including a thin-film transistor array defined in claim 1.

8. The thin-film transistor array as set forth in claim 1, wherein at least a part of each of said source, said drain, said pixel electrode, said source terminal and said gate terminal is comprised of a resistivity area having a carrier concentration higher than a carrier concentration of said channel.

9. The thin-film transistor array as set forth in claim 8, wherein the resistivity area has a resistivity which is equal to or greater than 1/10¹⁰, but equal to or smaller than 1/10² of a resistivity of said channel in equilibrium state in which no voltage is applied to said channel.

10. A thin-film transistor array comprising:

an electrically insulating substrate;

a plurality of thin-film transistors arranged in a matrix on said electrically insulating substrate, and each including a channel, a source and a drain each comprised of an oxide-semiconductor film;

a pixel electrode integrally formed with said drain;

a source signal line through which a source signal is transmitted to thin-film transistors located on a common column;

a gate signal line through which a gate signal is transmitted to thin-film transistors located on a common row;

a gate insulating layer formed above the gate signal line, the gate insulating layer having a get terminal contact hole;

a source terminal formed at an end of said source signal line; and

a gate terminal formed in said gate terminal contact hole in contact with said gate signal line at an end of said gate signal line,

said pixel electrode, being comprised of an oxide-semiconductor film composed of the same oxide semiconductor as the oxide-semiconductor film defining said channel and said source and drain,

said source terminal and said gate terminal being formed in the same layer of oxide-semiconductor film as a layer in which said channel, drain and source are formed.

11. The thin-film transistor array as set forth in claim 10, wherein said oxide-semiconductor film is composed of amorphous oxide containing at least one of Zn, Ga and In.

12. The thin-film transistor array as set forth in claim 10, wherein said oxide-semiconductor film is composed of crystalline oxide containing at least one of Zn, Ga and In.

13. The thin-film transistor array as set forth in claim 10, wherein said oxide-semiconductor film is composed of mixed crystal including both amorphous oxide containing at least one of Zn, Ga and In, and polycrystal oxide.

14. The thin-film transistor array as set forth in claim 13, wherein said crystalline oxide is formed by crystallizing amorphous oxide with laser irradiation thereto.

15. The thin-film transistor array as set forth in claim 10, wherein said oxide-semiconductor film is formed by dissolving powdered oxide semiconductor into solvent, coating or printing said solvent onto an object, and heating said solvent to vaporize said solvent.

16. The thin-film transistor array as set forth in claim 10, wherein said electrically insulating substrate is comprised of a resin substrate.

17. A liquid crystal display device including a thin-film transistor array defined in claim 10.

18. The thin-film transistor array as set forth in claim 10, wherein at least a part of each of said source, said drain, said pixel electrode, said source terminal and said gate terminal is comprised of a resistivity area having a carrier concentration higher than a carrier concentration of said channel.

19. The thin-film transistor array as set forth in claim 18, wherein the resistivity area has a resistivity which is equal to or greater than 1/10¹⁰, but equal to or smaller than 1/10² of a resistivity of said channel in equilibrium state in which no voltage is applied to said channel.