Method of semiconductor device protection, package of semiconductor device

• US 7,807,481 B2
• Filed: 04/24/2008
• Issued: 10/05/2010
• Est. Priority Date: 10/07/2003
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Maruyama, Shigeyuki, Kohashi, Naohito, Tashiro, Kazuhiro, Fukuda, Keisuke
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US12/081,961
• Publication Number:
  US 20080203558A1
• Time in Patent Office: 894 Days
• Field of Search: 438/11, 438/14, 438/18, 257/48, 257/704, 257/E21.521, 257/E21.524
• US Class Current: 438/14
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/67333 Trays for chips magazine for components H05K13/0084
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16153 Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/1616 Cavity shape
• CPC Class Codes: H01L 2924/166 Material
• CPC Class Codes: Y10T 29/49826 Assembling or joining

Abstract

A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Claims

1. A method for testing a semiconductor device, the semiconductor device including a plurality of semiconductor chips exposed thereon, the method comprising:

detachably attaching a semiconductor device protection cover to the semiconductor device, the semiconductor device protection cover touching the semiconductor device with a plurality of projections at free area where no semiconductor chip is provided on the semiconductor device, the free area being between the plurality of semiconductor chips, the semiconductor device protection cover having recesses over the plurality of semiconductor chips; and

testing the semiconductor device by pressing the semiconductor device against an IC contactor via the semiconductor device protection cover.

2. The method as claimed in claim 1, further comprising transporting the semiconductor device to which the semiconductor device protection cover is attached between the attaching and pressing.

3. The method as claimed in claim 1, wherein the semiconductor device protection cover is left attached to the semiconductor device after the test.