XFP transceiver with 8.5G CDR bypass
First Claim
Patent Images
1. A transceiver module, comprising:
- a TOSA;
a ROSA;
receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host;
transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and
bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate less than about 10 Gb/s, and wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is transmitted to or received from the host.
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Abstract
This disclosure concerns transceivers that include CDR bypass functionality. In one example, a 10 G XFP transceiver module includes integrated CDR functionality for reducing jitter. The 10 G XFP transceiver module also implements CDR bypass functionality so that the CDR can be bypassed at rate less than about 10 Gb/s, such as the Fibre Channel 8.5 Gb/s rate for example.
166 Citations
19 Claims
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1. A transceiver module, comprising:
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a TOSA; a ROSA; receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host; transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate less than about 10 Gb/s, and wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is transmitted to or received from the host. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A transceiver module, comprising:
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a plurality of components that are substantially compliant with the XFP MSA and are compatible for use in a Fibre Channel system, the plurality of components including; a TOSA; a ROSA; receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream at the first output is delivered to a host; transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate of about 8.5 Gb/s, wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is delivered to or received from the host. - View Dependent Claims (12, 13, 14, 15)
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16. A transceiver module, comprising:
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a TOSA; a ROSA; receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host; transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and bypass circuitry configured to enable at least one of the serial electrical data streams to automatically bypass corresponding eye opener circuitry if the corresponding eye opener circuitry is not locked onto that serial electrical data stream, wherein the corresponding eye opener circuitry is configured to lock onto data streams having a data rate of less than about 8.5 Gb/s. - View Dependent Claims (17, 18, 19)
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Specification