Depletion-mode MOSFET circuit and applications

  • US 7,817,459 B2
  • Filed: 01/24/2008
  • Issued: 10/19/2010
  • Est. Priority Date: 01/24/2007
  • Status: Active Grant
First Claim
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1. A static, random access memory device, comprising:

  • a memory cell comprising at least one depletion MOSFET transistor having a gate terminal coupled to a drain terminal, a substrate terminal coupled to a ground terminal/a positive voltage terminal and a source terminal coupled to a positive supply voltage terminal/a ground terminal; and

    an N type enhancement MOSFET transistor having a drain terminal coupled to said gate terminal of said at least one depletion MOSFET transistor, a substrate terminal coupled to said ground terminal, a source terminal coupled to a data line and a gate terminal coupled to an address line, thereby forming a two-transistor static, random access memory,wherein said depletion MOSFET transistor is an N type transistor having said substrate terminal coupled to said ground terminal and said source terminal coupled to said positive supply voltage terminal, thereby forming a two transistor static random access memory cell (2T(NN)-SRAM).

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