Generating a hardware description from a graphical program in response to receiving a diagram with states and state transitions

• US 7,818,715 B2
• Filed: 03/08/2007
• Issued: 10/19/2010
• Est. Priority Date: 12/20/2000
• Status: Expired due to Fees

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Hogan, Kevin
• Primary Examiner(s): Kang; Insun
• Application Number:
  US11/683,568
• Publication Number:
  US 20070150859A1
• Time in Patent Office: 1,321 Days
• Field of Search: None
• US Class Current: 717/109
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Claims

1. A method comprising:

receiving a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generating a data flow diagram based on the first diagram, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality; and

generating a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

2. The method of claim 1, wherein the data flow diagram is executable by a processor to perform the first functionality.

3. The method of claim 1, further comprising:

configuring the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements the hardware implementation of the data flow diagram.

4. The method of claim 1, wherein the first diagram corresponds to a desired algorithm.

5. The method of claim 1, wherein the first diagram corresponds to a test sequence.

6. The method of claim 1, wherein, for at least one state of the one or more states, the first diagram comprises program code associated with the at least one state;

wherein the automatically generated data flow diagram comprises the specified program code.

7. The method of claim 1, wherein, for at least one state, the first diagram comprises program code associated with the state;

wherein the automatically generated data flow diagram is operable to invoke the specified program code.

8. The method of claim 1, wherein the programmable hardware element comprises a field-programmable gate array (FPGA).

9. The method of claim 1, wherein the automatically generated data flow diagram comprises at least one placeholder for at least one state transition of the one or more transitions.

10. The method of claim 8, further comprising:

for the one or more state transitions, receiving user input specifying a Boolean condition associated with each state transition.

11. The method of claim 1, wherein the first diagram specifies at least two state transitions from a particular state;

wherein the first diagram also specifies a priority ordering for the at least two state transitions;

wherein said automatically generating comprises automatically generating the data flow diagram such that, during execution of the data flow diagram, conditions associated with the at least two state transitions are evaluated according to the specified priority ordering.

12. The method of claim 1, wherein the first diagram further specifies an initially active state;

wherein said automatically generating comprises automatically generating the data flow diagram such that the data flow diagram begins execution in the initially active state.

13. The method of claim 1, wherein the first diagram further specifies one or more stop states;

wherein said automatically generating comprises automatically generating the data flow diagram such that if during execution of the data flow diagram one of the stop states becomes active, then the data flow diagram is caused to stop execution.

14. The method of claim 1, further comprising:

receiving information specifying a change to the first diagram;

automatically updating the data flow diagram to reflect the specified change.

15. The method of claim 14, further comprising:

generating a new hardware configuration based on the data flow diagram, wherein the new hardware configuration is usable to configure the programmable hardware element and which reflects updated functionality of the data flow diagram.

16. The method of claim 1, wherein a first portion of the data flow diagram comprises a graphical user interface (GUI) for providing input to the data flow diagram and displaying output from the data flow diagram, and wherein the method further comprises compiling the first portion of the data flow diagram for execution on a processor to present the GUI on a display.

17. The method of claim 16, further comprising:

configuring the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the data flow diagram;

executing the first portion of the data flow diagram on the processor to present the GUI on the display;

receiving user input to the GUI;

providing the user input to the configured programmable hardware element; and

the configured programmable hardware element adjusting operation in response to the user input.

18. The method of claim 16, wherein the configured programmable hardware element is operable to adjust operation in response to the user input to the GUI.

19. The method of claim 1, wherein the plurality of nodes comprises at least one structure node, wherein the structure node represents control flow of data among one or more of the plurality of nodes.

20. The method of claim 19, wherein the structure node indicates iteration for the one or more of the plurality of nodes.

21. The method of claim 19, wherein the structure node indicates conditional branching for the one or more of the plurality of nodes.

22. The method of claim 19, wherein the structure node comprises a looping node, wherein the looping node indicates looping of the one or more of the plurality of nodes, wherein the looping node includes a loop condition which indicates a number of executions for the one or more of the plurality of nodes, and wherein said generating uses the loop condition in generating the hardware description.

23. The method of claim 19, wherein said generating the hardware description comprises converting each of said nodes into a hardware description format, and wherein for the structure node, said converting comprises:

determining inputs and outputs to/from the structure node;

creating a hardware description of a control block which performs the control function indicated by the structure node;

traversing input dependencies of the node; and

creating a hardware description of an AND gate including listing connections of the input dependencies of the node to the AND gate.

24. A memory medium comprising program instructions executable to:

receive a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generate a data flow diagram based on the first diagram, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality; and

generate a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

25. A system comprising:

a processor;

a memory medium coupled to the processor, wherein the memory medium comprises program instructions executable by the processor to;

receive a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generate a data flow diagram based on the first diagram, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality; and

generate a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

26. The system of claim 25, further comprising:

a programmable hardware element coupled to the processor and the memory medium;

wherein the program instructions are further executable to configure the programmable hardware element to produce a configured programmable hardware element, and wherein the configured programmable hardware element implements the hardware implementation of the data flow diagram.