On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol

• US 7,822,946 B2
• Filed: 02/04/2008
• Issued: 10/26/2010
• Est. Priority Date: 02/02/2007
• Status: Active Grant

• Current Assignee: Kiritin Incorporated
• Original Assignee: Psimast, Inc.
• Inventors: Sharma, Viswa
• Primary Examiner(s): Kim, Kenneth S
• Application Number:
  US12/025,720
• Publication Number:
  US 20080244150A1
• Time in Patent Office: 995 Days
• Field of Search: None
• US Class Current: 712/38
• CPC Class Codes: G06F 13/382 using universal interface adapter
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 12/56 Packet switching systems

Abstract

A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Claims

1. An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:

at least one processor core; and

at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide high speed packet switched serial interface for memory access to the at least processor core by encapsulating and decapsulating address, data and control information, using a packetized protocol for switched serial communication,

wherein the at least one processor core and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible,

such that the high-speed packet switched serial interface transfers the serialized protocol packet, to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol.

2. The apparatus of claim 1 further comprising:

a plurality of processor cores, each processor core with at least one packet processor uniquely associated therewith; and

at least one bridge interface operably connected to each packet processor and co-located on the semiconductor die package and adapted to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface.

3. The apparatus of claim 1 further comprising:

a plurality of processor cores, each processor core with at least one packet processor uniquely associated therewith; and

at least one switch interface operably connected to each packet processor and to the at least one external port and co-located on the semiconductor die package and adapted to mediate serial packetized communications among the packet processors and the at least one external port.

4. The apparatus of claim 2 wherein the at least one bridge interface is adapted with a switch to mediate communications between on-chip entities such as processor cores, caches, and the packet processor, as well as the communications between on-chip entities and off-chip devices such as the system main memory.

5. The apparatus of claim 1 wherein the packet processor is implemented as an on-the-fly programmable bit stream processor.

6. The apparatus of claim 1 wherein the high-speed packet switched serial interface is an Ethernet interface and the packet processor is adopted to support Ethernet protocol.

7. The apparatus of claim 1 wherein the high-speed packet switched serial interface is further adapted to transfer data from and to an external packet-switched network in addition to the system main memory.

8. The apparatus of claim 7 wherein the external packet-switched network is the Internet.

9. A method of implementing a computing and communication chip architecture for integrated circuitry, comprising:

providing a semiconductor die package having co-located thereon at least one processor core with at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface for memory access to the at least processor core by encapsulating and decapsulating address, data and control information, suing a packetized protocol for switched serial communication; and

utilizing the high-speed packet switched serial interface to transfer the serialized packet to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol.

10. The method of claim 9 further comprising:

providing a plurality of processor cores on the semiconductor die package, each processor core with at least one packet processor uniquely associated therewith; and

providing at least one bridge interface operably connected to each packet processor and co-located on the semiconductor die package; and

utilizing the at least one bridge interface to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface.

11. The method of claim 9 further comprising:

providing a plurality of processor cores on the semiconductor die package, each processor core with at least one packet processor uniquely associated therewith; and

providing at least one switch interface operably connected to each packet processor and to the at least one external port and co-located on the semiconductor die package; and

utilizing the at least one switch interface to mediate serial packetized communications among the packet processors and the at least one external port.

12. The method of claim 10 further comprising providing on the semiconductor die package the at least one bridge interface is adapted with a switch to mediate communications between on-chip entities such as processor cores, caches, and the packet processor, as well as the communications between on-chip entities and off-chip devices such as the system main memory.

13. The method of claim 9 wherein the high-speed packet switched serial interface further transfers data from and to an external packet-switched network in addition to the system main memory.

14. A computer readable media having recorded thereon instructions for implementing a computing and communication chip architecture for integrated circuitry on a semiconductor die package, comprising:

instructions defining at least one processor core co-located on the semiconductor die package with at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface for memory access to the at least processor core by encapsulating and decapsulating address data and control information using a packetized protocol for switched serial communication; and

instructions defining at least one external port to the semiconductor die package over which the high-speed packet switched serial interface is accessible,

such that the high-speed packet switched serial interface transfers the serialized protocol packet to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol.

15. The computer readable media of claim 14 further comprising:

instructions defining a plurality of processor cores on the semiconductor die package, each processor core with at least one packet processor uniquely associated therewith; and

instructions defining at least one bridge interface operably connected to each packet processor and co-located on the semiconductor die package adapted to be utilized to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface.

16. The computer readable media of claim 14 further comprising:

instructions defining a plurality of processor cores on the semiconductor die package, each processor core with at least one packet processor uniquely associated therewith; and

instructions defining at least one switch interface operably connected to each packet processor and to the at least one external port and co-located on the semiconductor die package to mediate serial packetized communications among the packet processors and the at least one external port.

17. The computer readable media of claim 14 further comprising instructions defining a cache memory for the at least one processor core adapted to be accessed via the associated at least packet processor for that processor core.

18. The computer readable media of claim 14 wherein the semiconductor die package is a field programmable gate array (FPGA) and the instructions are firmware adapted to configure the FPGA.

19. The computer readable media of claim 14 wherein the semiconductor die package is an application specific integrated circuit (ASIC) and the instructions are firmware adapted to configure the ASIC.