Array substrate for organic thin film transistor liquid crystal display device and method of manufacturing the same

• US 7,830,466 B2
• Filed: 08/24/2007
• Issued: 11/09/2010
• Est. Priority Date: 08/24/2006
• Status: Active Grant

• Current Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Naek Bong
• Primary Examiner(s): HEALY, BRIAN
• Application Number:
  US11/892,656
• Publication Number:
  US 20080049158A1
• Time in Patent Office: 1,173 Days
• Field of Search: 349/46, 349/43, 349/56, 349/58, 349/138, 349/139, 349/158, 349/122, 257/E21.535
• US Class Current: 349/46
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene

Abstract

An array substrate for an organic thin film transistor liquid crystal display device includes a substrate; a data line on the substrate; a first gate line crossing the data line to define a pixel region; an organic thin film transistor electrically connected to the first gate line and the data line, the organic thin film transistor including source and drain electrodes, an organic semiconductor layer on the source and drain electrodes, a gate electrode on the organic semiconductor layer; a pixel electrode in the pixel region and connected to the drain electrode; a gate pad terminal electrically connected to the first gate line and formed of a transparent conductive material; a data pad terminal electrically connected to the data line and formed of a transparent conductive material; and a passivation layer covering the organic thin film transistor and exposing the pixel electrode, the gate pad terminal, and the data pad terminal.

Claims

1. An array substrate for an organic thin film transistor liquid crystal display device, comprising:

a substrate;

a data line on the substrate;

a first gate line crossing the data line to define a pixel region;

an organic thin film transistor electrically connected to the first gate line and the data line, the organic thin film transistor including source and drain electrodes, an organic semiconductor layer on the source and drain electrodes, a gate electrode on the organic semiconductor layer;

a pixel electrode in the pixel region and connected to the drain electrode;

a gate pad terminal electrically connected to the first gate line and including a transparent conductive material;

a data pad terminal electrically connected to the data line and including a transparent conductive material; and

a passivation layer covering the organic thin film transistor and including a pixel opening, a gate pad contact hole and a data pad contact hole exposing the pixel electrode, the gate pad terminal, and the data pad terminal, respectively.

2. The array substrate according to claim 1, further comprising a connecting pattern on the passivation layer, wherein the connecting pattern connects the first gate line and the gate pad terminal.

3. The array substrate according to claim 1, further comprising a gate pad electrically connected to the first gate line, wherein the gate pad is formed of a same material and in a same layer as the data line, and the gate pad terminal covers the gate pad.

4. The array substrate according to claim 3, further comprising a data pad extending from the data line, wherein the data pad terminal covers the data pad.

5. The array substrate according to claim 1, wherein the gate electrode extends from the first gate line, and the organic semiconductor layer extends under the first gate line.

6. The array substrate according to claim 5, further comprising a gate insulating layer between the organic semiconductor layer and the gate electrode and between the organic semiconductor layer and the first gate line.

7. The array substrate according to claim 1, wherein the first gate line is disposed on the passivation layer and is connected to the gate electrode through a contact hole.

8. The array substrate according to claim 7, further comprising a gate pad electrically connected to the first gate line, wherein the gate pad is formed of a same material and in a same layer as the data line, and the gate pad terminal covers the gate pad.

9. The array substrate according to claim 1, wherein the pixel electrode overlaps a second gate line to constitute a storage capacitor.