Trench-constrained isolation diffusion for integrated circuit die

• US 7,834,416 B2
• Filed: 07/31/2008
• Issued: 11/16/2010
• Est. Priority Date: 08/14/2002
• Status: Expired due to Fees

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US12/221,105
• Publication Number:
  US 20080290452A1
• Time in Patent Office: 838 Days
• Field of Search: 257/330, 257/510, 257/513, 257/E29.201
• US Class Current: 257/513
• CPC Class Codes: H01L 21/8224 comprising a combination of vertical and lateral transistors
• CPC Class Codes: H01L 21/82285 Complementary vertical transistors
• CPC Class Codes: H01L 27/0821 Combination of lateral and vertical transistors only
• CPC Class Codes: H01L 27/0826 Combination of vertical complementary transistors
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate of a first conductivity type, said substrate not comprising an epitaxial layer;

first and second trenches formed in said substrate, said trenches filled with dielectric material; and

a region of a second conductivity type in said substrate formed in a mesa between said trenches, said region extending downward from a surface of said substrate and abutting respective sides of said trenches.

2. The semiconductor structure of claim 1 wherein said region of second conductivity type extends to a level in said substrate below a level of a bottom of each of said trenches.

3. A semiconductor structure comprising:

a semiconductor substrate of a first conductivity type, said substrate not comprising an epitaxial layer;

first and second trenches formed in said substrate, said trenches filled with dielectric material; and

a region of said first conductivity type in said substrate formed in a mesa between said trenches, a doping concentration of said region being greater than a doping concentration of said substrate, said region extending downward from a surface of said substrate and abutting respective sides of said trenches.

4. The semiconductor structure of claim 3 wherein said region of first conductivity type extends to a level in said substrate below a level of a bottom of each of said trenches.