Semiconductor memory device

• US 7,843,761 B2
• Filed: 06/10/2008
• Issued: 11/30/2010
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Yang, Sun-Suk, Kim, Yong-Ki
• Primary Examiner(s): Luu; Pho M
• Application Number:
  US12/136,513
• Publication Number:
  US 20090086564A1
• Time in Patent Office: 903 Days
• Field of Search: 365/230.08, 365/233.1, 365/230.01
• US Class Current: 365/230.08
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.

Claims

1. A semiconductor memory device, comprising:

an address buffering unit configured to buffer an input address;

a data input/output line configured to transfer data stored in a cell array;

a selecting unit configured to select, in response to operation modes of the device, one of the buffered input address and the transferred data as an output of the selecting unit and output the selected output; and

an output circuit configured to latch the selected output of the selecting unit as an output of the device.

2. The semiconductor memory device as recited in claim 1, wherein the address buffering unit is configured to buffer the input address to have an internal signal level of the device and synchronize buffered address with an internal clock.

3. The semiconductor memory device as recited in claim 1, wherein the selecting unit includes a multiplexer configured to receive the input address and the data.

4. The semiconductor memory device as recited in claim 3, wherein the multiplexer is configured to output the input address in a first of the operation modes and the data in a second of the operation modes, in response to a signal activated according to the operation modes.

5. The semiconductor memory device as recited in claim 4, wherein the multiplexer is configured to output the selected one of the address and the data in parallel according to a burst length of the device.

6. The semiconductor memory device as recited in claim 1, wherein the output circuit includes:

an output driver configured to latch the output of the selecting unit in series according to a burst length of the device; and

an output pin configured to output from the device an output of the output driver.

7. The semiconductor memory device as recited in claim 6, wherein the output pin includes a DQ pin of the device.

8. The semiconductor memory device as recited in claim 1, wherein the data input/output line includes a global input/output line of the device.

9. The semiconductor memory device as recited in claim 1, wherein the operation modes includes an address training mode and a normal mode.

10. A semiconductor memory device, comprising:

a selecting unit configured to select, in response to operation modes of the device, one of an output address received by the device and data stored in a cell array as an output of the selecting unit and output the selected output; and

an output circuit configured to output from the device the selected output of the selecting unit.

11. The semiconductor memory device as recited in claim 10, wherein the selecting unit includes a multiplexer.

12. The semiconductor memory device as recited in claim 11, wherein the selecting unit further includes:

an address buffering unit for buffering the address and synchronizing the buffered address with an internal clock as an output to the multiplexer; and

a data input/output line for transferring the data stored in the cell array to the multiplexer.

13. The semiconductor memory device as recited in claim 10, wherein the output circuit includes:

an output driver configured to latch the output of the selecting unit according to a burst length of the device; and

an output pin configured to output from the device an output of the output driver.

14. The semiconductor memory device as recited in claim 10, wherein the operation modes includes an address training mode and a normal mode.