System and method for recovery from memory errors in a medical device

• US 7,844,337 B2
• Filed: 12/27/2007
• Issued: 11/30/2010
• Est. Priority Date: 03/23/2004
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Hoyme, Kenneth P., Larson, Aaron
• Primary Examiner(s): KAHELIN, MICHAEL WILLIAM
• Application Number:
  US11/965,590
• Publication Number:
  US 20080103542A1
• Time in Patent Office: 1,069 Days
• Field of Search: 607/27, 607/31, 607/59
• US Class Current: 607/27
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit

Abstract

A system comprising an implantable medical device that comprises at least one electrical input to receive sensed electrical activity of a heart of a patient, a memory, and a controller circuit. The controller circuit is coupled to the electrical input and memory and is operable to enter a memory scrubbing mode that increases a rate of detecting and correcting single bit errors in the memory when the controller circuit determines the implantable device is in a high-energy radiation environment.

Claims

1. An apparatus comprising:

an implantable medical device comprising;

a memory; and

a controller circuit, coupled to the memory, wherein the controller circuit is configured to;

monitor a number of errors encountered while accessing memory locations in a normal operation mode, the monitoring including error checking all memory locations of the memory using a first rate of error checking per time period during the normal operation mode;

determine a rate of memory errors per time period using the monitored number of errors;

compare the rate of memory errors per time period to a programmable initiation threshold rate of memory errors per time period; and

when the rate of memory errors per time period exceeds the programmable initiation threshold error rate, then entering the memory scrubbing mode, wherein the memory scrubbing mode has an increased rate of error checking the memory locations of the memory per time period.

2. The apparatus of claim 1, wherein the controller circuit is configured to exit the memory scrubbing mode when the rate of memory errors per time period decreases below a programmable exit threshold rate of memory errors per time period.

3. The apparatus of claim 2, wherein the exit threshold rate of memory errors per time period is equal to the initiation threshold rate of memory errors per time period.

4. The apparatus of claim 2, wherein the controller circuit is configured to exit the scrubbing mode by gradually reducing a rate of error checking per time period until the controller circuit returns to the first rate of error checking per time period.

5. The apparatus of claim 1, wherein the implantable medical device includes a timer coupled to the controller circuit, and wherein the controller circuit is configured to exit the memory scrubbing mode after a predetermined time duration.

6. The apparatus of claim 1, wherein the controller circuit is configured to detect and correct single bit errors in the memory.

7. The apparatus of claim 1, wherein the controller circuit is configured to detect and correct multiple bit errors in the memory.

8. The apparatus of claim 1, wherein the implantable medical device further includes:

at least one output to provide therapy to the patient; and

a therapy circuit coupled to the at least one output and the controller circuit, the therapy circuit operable to deliver therapy to the patient.

9. The apparatus of claim 8, wherein the controller circuit is operable to execute instructions implementing the memory scrubbing mode at a lower priority than instructions related to therapy.

10. The apparatus of claim 8, wherein the controller circuit is configured to withhold therapy when the implantable medical device enters the memory scrubbing mode.

11. The apparatus of claim 1, comprising:

a sensing circuit coupled to the controller circuit to receive sensed electrical activity of a heart of a patient;

at least one electrical output to provide therapy to the heart;

a therapy circuit coupled to the at least one output, operable to deliver therapy to the heart; and

wherein the controller circuit is configured to provide therapy through the therapy circuit.

12. A method comprising:

monitoring a number of errors encountered while an implantable device is accessing memory locations in a normal operation mode, the monitoring including error checking all memory locations of the memory at a first rate of error checking per time period during the normal operation mode;

using the monitored number of errors to determine a rate of memory errors per time period;

comparing the rate of memory errors per time period to a programmable initiation threshold rate of memory errors per time period;

when the rate of memory errors per time period exceeds the programmable initiation threshold error rate, then entering a memory scrubbing mode; and

during the memory scrubbing mode, increasing a rate of error checking of the memory locations of the memory per time period to detect and correct memory errors in the implantable device.

13. The method of claim 12, including:

exiting the memory scrubbing mode when the rate of memory errors decreases below a programmable exit threshold rate of memory errors per time period; and

returning to a lower rate of detecting and correcting memory errors in the device.

14. The method of claim 12, including:

exiting the memory scrubbing mode when the rate of memory errors per time period decreases below the initiation threshold rate of memory errors per time period; and

returning to a lower rate of detecting and correcting memory errors in the device.

15. The method of claim 12, including:

exiting the memory scrubbing mode when a duration of the memory scrubbing mode in the implantable medical device exceeds a specified duration; and

returning to a lower rate of detecting and correcting memory errors in the device.

16. The method of claim 12, including:

exiting the memory scrubbing mode when the rate of memory errors decreases below a programmable exit threshold rate of memory errors per time period; and

gradually reducing a rate of error checking per time period until the controller circuit returns to the first rate of error checking per time period.

17. The method of claim 12, including:

delivering therapy to a patient in the normal operation mode; and

executing instructions to implement the memory scrubbing mode at a lower priority than instructions related to therapy.

18. The method of claim 12, including:

delivering therapy to a patient in the normal operation mode; and

withholding therapy when the implantable medical device enters the memory scrubbing mode.

19. An apparatus comprising:

means for;

monitoring a number of errors encountered while accessing memory locations in a normal operation mode, the monitoring including error checking all memory locations of the memory at a first rate of error checking per time period during the normal operation mode;

using the monitored number of errors per time period to determine a rate of memory errors per time period;

comparing the rate of memory errors per time period to a programmable threshold rate of memory errors per time period; and

detecting that the rate of memory errors per time period exceeds the programmable threshold error rate per time period;

means for enabling a memory scrubbing mode in response to the implantable medical device detecting that the rate of memory errors per time period exceeds the programmable threshold error rate; and

means for increasing a rate of error checking of the memory locations of the memory per time period during the memory scrubbing mode to detect and correct memory errors in the device upon the enabling of the scrubbing mode.

20. The apparatus of claim 19, including:

means for exiting the memory scrubbing mode when the rate of memory errors decreases below the programmable threshold rate of memory errors per time period; and

means for gradually reducing a rate of error checking per time period until the controller circuit returns to the first rate of error checking per time period.