System and method for TCP offload

• US 7,849,208 B2
• Filed: 02/18/2008
• Issued: 12/07/2010
• Est. Priority Date: 08/30/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Elzur, Uri, McDaniel, Scott S., Fan, Frankie, Lindsay, Steven B.
• Primary Examiner(s): Chan; Wing F
• Assistant Examiner(s): KATSIKIS, KOSTAS J
• Application Number:
  US12/032,953
• Publication Number:
  US 20080151922A1
• Time in Patent Office: 1,023 Days
• Field of Search: None
• US Class Current: 709/232
• CPC Class Codes: H04L 47/193 at the transport layer, e.g. TCP related
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A system for processing packets is disclosed and may including a network interface card (NIC). The NIC may include a TCP enabled Ethernet controller (TEEC). The TEEC may include an internal elastic buffer. The TEEC may process received incoming TCP packets once and may temporarily buffer at least a portion of the incoming TCP packets in the internal elastic buffer. The processing may occur without reassembly or retransmission. The internal elastic buffer may include a receive internal elastic buffer and a transmit internal elastic buffer. The receive internal elastic buffer may temporarily buffer at least a portion of the received incoming TCP packets. The transmit internal elastic buffer may temporarily buffer at least a portion of TCP packets to be transmitted. The TEEC may place at least a portion of the received incoming TCP packets data into at least a portion of a host memory.

Claims

1. A system for processing packets during communication, the system comprising:

one or more circuits comprising a Transmission Control Protocol (TCP) enabled Ethernet controller (TEEC) and an internal elastic buffer within said TEEC, wherein said one or more circuits receives incoming TCP packets by said TEEC; and

said one or more circuits temporarily buffers at least a portion of said received incoming TCP packets in said internal elastic buffer and processes said at least a portion of said buffered received incoming TCP packets once by said TEEC without reassembly or retransmission by said TEEC.

2. The system according to claim 1, wherein said internal elastic buffer comprises a receive internal elastic buffer and a transmit internal elastic buffer.

3. The system according to claim 2, wherein said one or more circuits enables temporary buffering of said at least a portion of said received incoming TCP packets in said receive internal elastic buffer.

4. The system according to claim 2, wherein said one or more circuits enables temporary buffering of at least a portion of TCP packets to be transmitted, in said transmit internal elastic buffer.

5. The system according to claim 1, wherein said one or more circuits places at least a portion of said processed at least a portion of said buffered incoming TCP packets in host memory.

6. The system according to claim 1, wherein said one or more circuits copies at least a portion of said processed at least a portion of said buffered incoming TCP packets to host memory via a single copy operation.

7. The system according to claim 1, wherein said one or more circuits places at least a portion of said processed at least a portion of said buffered incoming TCP packets in a highest hierarchy of buffer available in a host memory.

8. The system according to claim 1, wherein said one or more circuits enables DMA transfer of at least a portion of said processed at least a portion of said buffered incoming TCP packets to a host memory.

9. The system according to claim 1, wherein packets temporarily buffered in said internal elastic buffer are not buffered to enable reassembly by said TEEC.

10. The system according to claim 1, wherein packets temporarily buffered in said internal elastic buffer are not buffered to enable retransmission by said TEEC.

11. The system according to claim 1, wherein said one or more circuits places at least a portion of said processed at least a portion of said buffered incoming TCP packets at least a portion of said processed incoming TCP packet in host buffers in a host memory for processing.

12. The system according to claim 1, wherein said one or more circuits are integrated within a single chip.

13. The system according to claim 1, wherein said one or more circuits are integrated within network interface card (NIC).

14. A system for processing packets, the system comprising:

a network interface card (NIC), said NIC comprising;

a Transmission Control Protocol (TCP) enabled Ethernet controller (TEEC), said TEEC comprising,

an internal elastic buffer, wherein said TEEC processes received incoming TCP packets once and temporarily buffers at least a portion of said incoming TCP packets in said internal elastic buffer, wherein said processing occurs without reassembly or retransmission.

15. The system according to claim 14, wherein said internal elastic buffer comprises a receive internal elastic buffer and a transmit internal elastic buffer.

16. The system according to claim 15, wherein said receive internal elastic buffer temporarily buffers at least a portion of said received incoming TCP packets.

17. The system according to claim 15, wherein said transmit internal elastic buffer temporarily buffers at least a portion of TCP packets to be transmitted.

18. The system according to claim 14, wherein said TEEC places at least a portion of said received incoming TCP packets data into at least a portion of a host memory.

19. The system according to claim 14, wherein said NIC utilizes only said internal elastic buffer to temporarily buffer said at least a portion of said received incoming TCP packets.

20. The system according to claim 14, wherein out-of-order TCP packets within said received incoming TCP packets are not stored, re-ordered and/or re-assembled by said TEEC.

21. The system according to claim 14, wherein said NIC does not require a dedicated memory for re-ordering out-of-sequence TCP packets within said received incoming TCP packets.

22. The system according to claim 14, wherein said NIC does not require a dedicated memory for assembling and/or re-ordering IP packets fragmented at an IP layer.

23. The system according to claim 14, wherein said TEEC is enabled to place at least data from said received incoming TCP packets into a highest hierarchy of buffer available in a host memory.

24. The system according to claim 14, wherein said TEEC is enabled to copy at least data from said received incoming TCP packets to a buffer in host memory via a single copy operation.

25. The system according to claim 14, wherein said TEEC is enabled to DMA transfer at least a portion of said processed incoming TCP packets to a host memory.

26. The system according to claim 14, wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet retransmission.

27. The system according to claim 14, wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet reassembly.

28. The system according to claim 14, wherein said TEEC places at least a portion of said processed received incoming TCP packets into host buffers in a host memory for reassembly.

29. The system according to claim 14, wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer.

30. The system according to claim 14, wherein said NIC comprises a single chip, having integrated therein, said TEEC and said internal elastic buffer.

31. The system according to claim 14, wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer, and no internal buffers and interfaces to external buffers that are utilized for packet retransmission, packet reassembly and/or packet re-ordering.

32. A method for processing packets, the method comprising:

in a Transmission Control Protocol (TCP) enabled Ethernet controller (TEEC), temporarily buffering at least a portion of received incoming TCP packets in an elastic buffer internal to said TEEC, wherein said TEEC is integrated within a network interface card (NIC); and

processing said temporarily buffered received incoming TCP packets once without reassembly or retransmission.

33. The method according to claim 32, wherein said internal elastic buffer comprises a receive internal elastic buffer and a transmit internal elastic buffer.

34. The method according to claim 33, wherein said receive internal elastic buffer temporarily buffers at least a portion of said received incoming TCP packets.

35. The method according to claim 33, wherein said transmit internal elastic buffer temporarily buffers at least a portion of TCP packets to be transmitted.

36. The method according to claim 32, comprising placing by said TEEC, at least a portion of said received incoming TCP packets data into at least a portion of a host memory.

37. The method according to claim 32, wherein said NIC utilizes only said internal elastic buffer to temporarily buffer said at least a portion of said received incoming TCP packets.

38. The method according to claim 32, wherein out-of-order TCP packets within said received incoming TCP packets are not stored, re-ordered and/or re-assembled by said TEEC.

39. The method according to claim 32, wherein said NIC does not require a dedicated memory for re-ordering out-of-sequence TCP packets within said received incoming TCP packets.

40. The method according to claim 32, wherein said NIC does not require a dedicated memory for assembling and/or re-ordering IP packets fragmented at an IP layer.

41. The method according to claim 32, comprising placing by said TEEC, at least data from said received incoming TCP packets into a highest hierarchy of buffer available in a host memory.

42. The method according to claim 32, comprising copying by said TEEC, at least data from said received incoming TCP packets to a buffer in host memory via a single copy operation.

43. The method according to claim 32, comprising DMA transferring by said TEEC, at least a portion of said processed incoming TCP packets to a host memory.

44. The method according to claim 32, wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet retransmission.

45. The method according to claim 32, wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet reassembly.

46. The method according to claim 32, comprising placing by said TEEC, at least a portion of said processed received incoming TCP packets into host buffers in a host memory for reassembly.

47. The method according to claim 32, wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer.

48. The method according to claim 32, wherein said NIC comprises a single chip, having integrated therein, said TEEC and said internal elastic buffer.

49. The method according to claim 32, wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer, and no internal buffers and interfaces to external buffers that are utilized for packet retransmission, packet reassembly and/or packet re-ordering.

50. A system for processing packets during communication, the system comprising:

an Ethernet controller operable to process TCP packets without reassembly or retransmission; and

an internal elastic buffer within the Ethernet controller operable to temporarily store TCP packets,

wherein at least one TCP packet is buffered prior to being processed,

wherein the size of the buffer is variable, and

wherein the size of the buffer is based on at least the rate of TCP packet arrival.

51. The system according to claim 50, wherein the Ethernet controller places at least a portion of the processed TCP packets in host memory.

52. The system according to claim 50, wherein the Ethernet controller copies at least a portion of the processed TCP packets to host memory via a single copy operation.

53. The system according to claim 50, wherein the Ethernet controller places at least a portion of the processed TCP packets in a hierarchy of buffers available in a host memory, wherein the placement is based on packet priority.

54. The system according to claim 50, wherein the Ethernet controller enables DMA transfer of at least a portion of the processed TCP packets to host memory.

55. The system according to claim 50, wherein temporarily buffered TCP packets are not buffered to enable reassembly.

56. The system according to claim 50, wherein temporarily buffered TCP packets are not buffered to enable retransmission.

57. The system according to claim 50, wherein the Ethernet controller and buffer are integrated within a single chip.

58. The system according to claim 50, wherein the Ethernet controller and buffer are integrated within a network interface card (NIC).