Bonding structures and methods of forming bonding structures

• US 7,851,331 B2
• Filed: 11/27/2006
• Issued: 12/14/2010
• Est. Priority Date: 11/27/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lii, Mirng-Ji, Lu, Szu Wei, Chen, Chen-Shien, Wu, Hua-Shu, Tzou, Jerry
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Tran; Tony
• Application Number:
  US11/563,490
• Publication Number:
  US 20080122114A1
• Time in Patent Office: 1,478 Days
• Field of Search: 438/459, 257618-628
• US Class Current: 438/459
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4809 : Loop shape
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48095 : Kinked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 : the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/495 : Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.

Claims

1. A method of forming a semiconductor structure, comprising:

bonding a dummy substrate over a first substrate, the first substrate comprising a passivation layer formed thereover, the passivation layer comprising at least one first opening in which a first bonding pad is formed, the first opening having a first sidewall surrounding the first opening, the dummy substrate comprising at least one second opening therein before bonding the dummy substrate over the first substrate, the second opening having a second sidewall surrounding the second opening and a base, the second sidewall being unconnected to the first sidewall before bonding the dummy substrate, the second opening aligned with and facing the first opening;

thinning the first substrate using the dummy substrate as a carrier for the first substrate; and

thinning the dummy substrate to remove the base and expose the first opening through the second opening, without removing the entire dummy substrate.

2. The method of claim 1, wherein the bonding step comprises a fusion bonding step.

3. The method of claim 2 further comprising forming at least one through wafer via (TWV) in the thinned first substrate.

4. The method of claim 3 further comprising:

mounting the thinned first substrate over a second substrate, the second substrate comprising at least one second bonding pad formed thereover; and

wire bonding the first bonding pad to the second bonding pad through the first opening and the second opening.

5. The method of claim 4, wherein the second substrate is a lead frame substrate for a radio frequency device.

6. The method of claim 1 further comprising

mounting the thinned first substrate over a second substrate, the second substrate comprising at least one second bonding pad formed thereover;

and

wire bonding the first bonding pad to the second bonding pad through the first opening and the second opening.

7. The method of claim 1 further comprising dicing the first substrate with the thinned dummy substrate bonded thereover, thereby forming a plurality of individual dies.

8. The method of claim 1, wherein the second opening is substantially equal to or larger than the first opening in area.

9. The method of claim 1, wherein the thinning step includes removing an entire portion of the dummy substrate extending from the base to a back surface of the dummy substrate opposite a surface having the second opening therein, so that the second opening extends through an entire thickness of the dummy substrate after the thinning.

10. The method of claim 1, wherein the first and second openings are substantially equal to each other in width, length and/or diameter.

11. A method of forming a semiconductor structure, comprising:

providing a first substrate comprising a passivation layer formed thereover, the passivation layer comprising at least one first opening in which a first bonding pad is formed, the first opening having a first sidewall surrounding the first opening;

providing a dummy substrate separate from the first substrate, the dummy substrate comprising at least one second opening having a base and sidewall surrounding the second opening, the second sidewall being unconnected to the first sidewall;

fusion bonding the dummy substrate over the first substrate, so that the at least one second opening in the dummy substrate is aligned with and facing the first opening in the first substrate;

thinning the first substrate using the dummy substrate as a carrier for the first substrate; and

thinning the dummy substrate to remove the base and expose the first opening through the second opening, without removing the entire dummy substrate.

12. The method of claim 11, further comprising:

mounting the thinned first substrate over a second substrate, the second substrate comprising at least one second bonding pad formed thereover;

wire bonding the first bonding pad to the second bonding pad through the first opening and the second opening.

13. The method of claim 12, wherein the second substrate is a lead frame substrate for a radio frequency device, the second substrate has a first portion over which the thinned first substrate is mounted, and at least one second portion on which the second bonding pad is formed, the second portion being isolated from the first portion.

14. The method of claim 11, further comprising forming at least one through wafer via (TWV) in the thinned first substrate.

15. The method of claim 11, wherein the thinning step includes removing an entire portion of the dummy substrate extending from the base to a back surface of the dummy substrate opposite a surface having the second opening therein, so that the second opening extends through an entire thickness of the dummy substrate after the thinning.

16. The method of claim 11, wherein the first and second openings are substantially equal to each other in width, length and/or diameter.