Hierarchical interface for IC system

• US 7,852,117 B1
• Filed: 07/17/2009
• Issued: 12/14/2010
• Est. Priority Date: 07/17/2009
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lo, Jack S., Brebner, Gordon J., Neely, Christopher E.
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US12/505,239
• Time in Patent Office: 515 Days
• Field of Search: None
• US Class Current: 326/62
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

An integrated circuit includes an auto-bridging architecture including a first phases block that interfaces to a first user block having a first user signal domain. The first phases block converts the first user signal domain to a common signal domain. A second phases block coupled to the first phases block interfaces with a second user block having a second user signal domain. The second phases block converts the second user signal domain to the common signal domain so that the first user block cooperates with the second user block through the auto-bridging architecture of the IC.

Claims

1. An integrated circuit (“

IC”

), comprising;

an auto-bridging architecture including

a first phases block interfacing to a first user block having a first user signal domain, the first phases block configured to convert the first user signal domain to a common signal domain; and

a second phases block coupled to the first phases block and interfacing with a second user block having a second user signal domain, the second phases block configured to convert the second user signal domain to the common signal domain, the first user block cooperating with the second user block through the auto-bridging architecture of the IC.

2. The IC of claim 1, wherein the first phases block includes a first code translator translating a first signal from the first user block to an event in the common signal domain and generating an assert signal coupled to the second phases block.

3. The IC of claim 2, wherein the second phases block includes a second code translator translating the event to a second signal coupled to the second user block.

4. The IC of claim 2, wherein the first phases block further includes a first phase register and the second phases block further includes a second phase register, the first phase register passing data to the second phase register through the common signal domain.

5. The IC of claim 1, further comprising an intermediate component in the common signal domain disposed between the first phases block and the second phases block.

6. The IC of claim 5, wherein the intermediate component includes a phase replicator.

7. The IC of claim 6, wherein the intermediate component further includes an address register disposed between a first phase register in the first phases block and a second phase register in the second phases block.

8. The IC of claim 5, wherein the first user signal domain has a first data width and a first clock domain, and the second user signal domain has a second data width or a second clock domain.

9. The IC of claim 1, wherein the IC is a field-programmable gate array and the auto-bridging architecture is configured in the field-programmable gate array.

10. The IC of claim 9, wherein the first user block is also configured in the field-programmable gate array.

11. A method of designing the IC of claim 1 in accordance with the following steps:

modeling a first interface of a first user block including translating first interface attributes to a first behavioral interface definition, further defining the first behavioral interface definition in a first coding and timing layer, and mapping the first coding and timing layer to a first signal layer to produce a first hierarchical interface model;

modeling a second interface of a second user block in a second hierarchical interface model including translating second interface attributes to a second behavioral interface definition, further defining the second behavioral interface definition in a second coding and timing layer of the second interface in the second hierarchical interface model, and mapping the second coding and timing layer to a second signal layer of the second hierarchical interface model;

comparing the first hierarchical interface model with the second hierarchical model in a common signal domain; and

resolving an interface connection between the first user block and the second user block,

wherein the comparing and resolving are performed by a computer.