Liquid crystal display and thin film transistor array panel usable with the liquid crystal display

• US 7,852,444 B2
• Filed: 10/06/2005
• Issued: 12/14/2010
• Est. Priority Date: 10/06/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Jang-Kun
• Primary Examiner(s): Nelms; David
• Assistant Examiner(s): Chien; Lucy P
• Application Number:
  US11/245,679
• Publication Number:
  US 20060072049A1
• Time in Patent Office: 1,895 Days
• Field of Search: None
• US Class Current: 349/141
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel

Abstract

A liquid crystal display with improved viewing angle and uncompromised transmittance is provided, along with a thin film transistor (TFT) array panel usable for such liquid crystal display. The TFT array panel includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines formed on the substrate and intersecting the gate lines, and a plurality of thin film transistors. Each of the thin film transistors includes a gate electrode connected to one of the gate lines, a source electrode connected to one of the data lines, and a drain electrode. The TFT array panel also includes a plurality of pixel electrodes, each of the pixel electrodes connected to one of the drain electrodes and having a pair of oblique edges parallel to each other, and covering at least a portion of the drain electrodes.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a plurality of gate lines formed on the substrate;

a plurality of data lines formed on the substrate and intersecting the gate lines;

a gate insulating layer formed on the gate lines;

a plurality of thin film transistors, each of the thin film transistors including a gate electrode connected to one of the gate lines, a source electrode connected to one of the data lines, and a drain electrode;

a plurality of color filters formed on the thin film transistor and the gate insulating layer;

a passivation layer formed on the color filters; and

a plurality of pixel electrodes formed on the passivation layer, each of the pixel electrodes connected to one of the drain electrodes, each of the pixel electrodes having a generally chevron shape and covering at least a portion of the data line such as to form a fully-covered segment and a non-covered segment of the data line, wherein a width of the fully-covered segment of the data line is fully covered by the chevron shape of the pixel electrode.

2. The thin film transistor array panel of claim 1, wherein each of the data lines overlaps two adjacent pixel electrodes.

3. The thin film transistor array panel of claim 1, wherein each of the pixel electrodes overlaps two data lines.

4. The thin film transistor array panel of claim 3, wherein an overlapping area between each of the pixel electrodes and one of the two data lines is equal to about a half of to about twice an overlapping area between each of the pixel electrodes and the other of the two data lines.

5. The thin film transistor array panel of claim 3, wherein each of the data lines comprises a pair of bent portions disposed between two adjacent gate lines and overlapping the pixel electrodes.

6. The thin film transistor array panel of claim 5, wherein each of the data lines further comprises a linear portion connected to the bent portions of the data line and overlapping the pixel electrodes.

7. The thin film transistor array panel of claim 3, wherein each of the data lines comprises a portion disposed between two adjacent gate lines and bending at least twice.

8. The thin film transistor array panel of claim 7, wherein the bent portions of the data lines are equidistant from the oblique edges of the pixel electrodes.

9. The thin film transistor array panel of claim 1, wherein each of the data lines includes a linear oblique portion that is parallel to the oblique edges of the pixel electrodes and overlapping the pixel electrodes.

10. The thin film transistor array panel of claim 1, wherein each of the data lines includes a bent portion extending substantially parallel to the oblique edges of the pixel electrodes and a linear portion intersecting the gate lines.

11. The thin film transistor array panel of claim 10, wherein the bent portion of each of the data lines comprises a pair of linear oblique portions extending to make an angle of about 45 degrees with the gate lines.

12. The thin film transistor array panel of claim 11, wherein the bent portions of the data lines overlap the pixel electrodes.

13. The thin film transistor array panel of claim 11, wherein the bent portions of the data lines are disposed near centers of the pixel electrodes and covered with the pixel electrodes.

14. The thin film transistor array panel of claim 11, further comprising a plurality of storage electrode lines including storage electrodes that overlap the drain electrodes.

15. The thin film transistor array panel of claim 14, wherein the storage electrode lines further comprise branches disposed between the pixel electrodes and partially overlapping the pixel electrodes.

16. The thin film transistor array panel of claim 15, wherein the color filters partially overlap the branches of the storage electrode lines and overlapping the pixel electrodes.

17. The thin film transistor array panel of claim 1, wherein the data lines have a width of about four microns to about eight microns.