Method for forming polycrystalline thin film bipolar transistors

• US 7,855,119 B2
• Filed: 06/15/2007
• Issued: 12/21/2010
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J., Herner, S. Brad
• Primary Examiner(s): Smith; Matthew S
• Assistant Examiner(s): FAN, SU JYA
• Application Number:
  US11/763,876
• Publication Number:
  US 20080311722A1
• Time in Patent Office: 1,285 Days
• Field of Search: 438/378, 438/309, 438/350, 438/342, 257/E21.37, 257/E21.372, 257/E29.171, 257/E27.053, 257/E27.055, 257/565, 257/590, 257/591, 257/592, 257/593
• US Class Current: 438/378
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 29/66265 Thin film bipolar transistors H01L29/66242 takes precedence
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors

Abstract

A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49phase titanium silicide.

Claims

1. A method of forming a bipolar transistor comprising the steps of:

depositing a layer of amorphous semiconductor material comprising silicon, germanium, or silicon-germanium above a substrate;

depositing a metal in contact with the amorphous semiconductor material;

forming a crystallization template by annealing to react the metal with the amorphous semiconductor material, wherein the crystallization template layer comprises metal silicide, metal germanide or metal silicide-germanide; and

crystallizing the layer of amorphous semiconductor material using the crystallization template, wherein the bipolar transistor comprises a base region, a collector region and an emitter region formed in the crystallized semiconductor material; and

doping the emitter and collector regions with a p-type dopant to form a p-n-p bipolar transistor.

2. The method of claim 1 wherein the metal comprises titanium or cobalt.

3. The method of claim 1 wherein the metal comprises titanium.

4. The method of claim 1 wherein the semiconductor material comprises silicon.

5. The method of claim 1 wherein the semiconductor material comprises germanium.

6. The method of claim 1 wherein the semiconductor material comprises silicon-germanium.

7. The method of claim 1 wherein the annealing step is done by a rapid thermal anneal.

8. The method of claim 1 wherein the bipolar transistor is operatively connected to a first plurality of memory cells formed above the substrate.

9. The method of claim 8 wherein each of the first plurality of memory cells comprises the crystallized semiconductor material.

10. The method of claim 8 wherein the bipolar transistor is capable of selectively programming one or more of the first plurality of memory cells.

11. The method of claim 8 further comprising the step of applying a programming voltage to the bipolar transistor to program one or more of the first memory cells.

12. The method of claim 1 wherein the bipolar transistor is operatively connected to control circuitry disposed in the substrate.

13. The method of claim 1 wherein the substrate is a portion of a monocrystalline silicon wafer.

14. A method for making a thin film bipolar transistor comprising the steps of:

depositing a layer of amorphous silicon above a substrate;

doping a first portion and a second portion of the amorphous silicon layer with a p-type or n-type dopant;

depositing a layer of silicide-forming metal adjacent to the amorphous silicon layer; and

thermally annealing to react the metal and the amorphous silicon layer to form a metal silicide and to crystallize the amorphous silicon layer to polysilicon, wherein the bipolar transistor has a collector region and an emitter region corresponding to the p-type or n-type doped first and second portions of the polysilicon and a base region formed in the polysilicon.

15. The method of claim 14 wherein the silicide-forming metal is titanium.

16. The method of claim 14 wherein the metal silicide is titanium silicide.

17. The method of claim 16 wherein the titanium silicide is predominantly C49 phase titanium silicide.