Semiconductor device and method of fabricating the same

• US 7,858,480 B2
• Filed: 02/20/2009
• Issued: 12/28/2010
• Est. Priority Date: 02/21/2008
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamasaki, Hiroyuki
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): SCARLETT, SHAKA S
• Application Number:
  US12/390,033
• Publication Number:
  US 20090212372A1
• Time in Patent Office: 676 Days
• Field of Search: None
• US Class Current: 438/279
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films; two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes; a source/drain region formed in a region of the semiconductor substrate sandwiching the two channel regions; a first stress film formed so as to cover the semiconductor substrate and the two gate electrodes; and a second stress film formed in at least a portion of a void, the void being formed in a region between the two gate electrodes.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising an element isolation region;

first and second gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films;

first and second channel regions respectively formed in regions of the semiconductor substrate under the first and second gate electrodes;

a source/drain region formed in a region of the semiconductor substrate sandwiching the first and second channel regions;

a first stress film formed so as to cover the semiconductor substrate and the first and second gate electrodes; and

a second stress film formed in at least a portion of a void, the void being formed in a region between the first and second gate electrodes, the void being formed in the first stress film or in an interlayer insulating film formed on the first stress film.

2. The semiconductor device according to claim 1, wherein the element isolation region comprises concave portions in regions between the first and second gate electrodes;

and

at least a portion of the first stress film is formed in the concave portions above the element isolation region.

3. The semiconductor device according to claim 1, wherein first and second gate sidewalls are respectively formed on side faces of the first and second gate electrodes;

and

the first stress film is formed so as to cover the semiconductor substrate, the first and second gate electrodes and the first and second gate sidewalls.

4. The semiconductor device according to claim 3, wherein an angle of the side faces of the first and second gate sidewalls is substantially orthogonal to a surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein a contact penetrating through the void is formed on the source/drain region, the contact connecting an upper wiring with the source/drain region.

6. The semiconductor device according to claim 1, wherein a dummy contact penetrating through the void is formed on the element isolation region.

7. The semiconductor device according to claim 2, wherein a dummy contact penetrating through the void is formed on one of the concave portions in the element isolation region.

8. The semiconductor device according to claim 1, wherein the first and second gate electrodes, the first and second channel regions and the source/drain region constitute an n-type transistor;

and

the first and second stress films include a stress for generating a tensile stress in a channel direction in the first and second channel regions.

9. The semiconductor device according to claim 1, wherein the source/drain region between the first and second gate electrodes is shared by transistors each composed of the first and second gate electrodes.

10. The semiconductor device according to claim 1, comprising a SRAM structure formed on the semiconductor substrate and comprising the first and second gate electrodes, the first and second channel regions, the source/drain region and the first and second stress films.

11. The semiconductor device according to claim 1, wherein the source drain region is a first source/drain region, the semiconductor device further comprising:

the first and second gate electrodes formed on the semiconductor substrate in an n-type transistor region;

first and second gate sidewalls respectively formed on side faces of the first and second gate electrodes;

the first and second channel regions formed in the n-type transistor region;

the first source/drain region formed in the n-type transistor region;

the first stress film formed so as to cover the semiconductor substrate and the first and second gate electrodes in the n-type transistor region, and including a stress for generating a tensile stress in a channel direction in the first and second channel regions;

the second stress film formed in the n-type transistor region and including a stress for generating a tensile stress in the channel direction in the first and second channel regions;

third and fourth gate electrodes formed in substantially parallel on the semiconductor substrate in a p-type transistor region via respective gate insulating films;

third and fourth gate sidewalls having a taper shape formed on side faces of the third and fourth gate electrodes;

third and fourth channel regions respectively formed in regions of the semiconductor substrate under the third and fourth gate electrodes in the p-type transistor region;

a second source/drain region formed in a region of the semiconductor substrate sandwiching the third and fourth channel regions in the p-type transistor region; and

a third stress film formed so as to cover the semiconductor substrate and the third and fourth gate electrodes in the p-type transistor region, and including a stress for generating a compressive stress in a channel direction in the third and fourth channel regions.

12. A method of fabricating a semiconductor device, comprising:

forming two gate electrodes in substantially parallel on a semiconductor substrate via respective gate insulating films;

forming a source/drain region in the semiconductor substrate on both sides of the two gate electrodes;

forming a first stress film on the semiconductor substrate and the two gate electrodes;

forming an interlayer insulating film on the first stress film;

forming a contact hole in the first stress film and the interlayer insulating film on the source/drain region so as to penetrate through a void, the void being in the first stress film or the interlayer insulating film in a region between the two gate electrodes; and

forming a second stress film in at least a portion of the void via the contact hole.

13. The method of fabricating a semiconductor device according to claim 12, wherein the first stress film is formed by a plasma CVD method.

14. The method of fabricating a semiconductor device according to claim 12, wherein the interlayer insulating film is formed by a CVD method using TEOS.

15. The method of fabricating a semiconductor device according to claim 12, wherein the second stress film is formed by a LPCVD method.

16. The method of fabricating a semiconductor device according to claim 12, wherein gate sidewalls are each formed on the side faces of the two gate electrodes;

and

a first stress film is formed on the semiconductor substrate, the two gate electrodes and the gate sidewalls.

17. The method of fabricating a semiconductor device according to claim 12, wherein a dummy contact hole is formed together with the contact hole in the first stress film and the interlayer insulating film on an element isolation region in the semiconductor substrate so as to penetrate through a void in the first stress film or the interlayer insulating film in a region between the two gate electrodes;

and

the second stress film is formed in at least a portion of the void via the contact hole and the dummy contact hole.

18. The method of fabricating a semiconductor device according to claim 12, wherein a concave portion is formed by etching a region between the two gate electrodes in the element isolation region in the semiconductor substrate;

and

the first stress film is formed on the semiconductor substrate, the concave portion of the element isolation region and the two gate electrodes.

19. The method of fabricating a semiconductor device according to claim 12, wherein a first insulating film and a second insulating film are deposited on the semiconductor substrate and the two gate electrodes after forming the source/drain region, a portion of the second insulating film located on an upper surface of the first insulating film is removed by etching, then, an anisotropic etching process in a direction substantially orthogonal to a surface of the semiconductor substrate is applied to the first and second insulating films, thereby forming the first insulating film shaped into gate sidewalls on side faces of the two gate electrodes, the gate sidewalls having side faces formed with an angle substantially orthogonal to the surface of the semiconductor substrate;

and

the first stress film is formed on the semiconductor substrate, the two gate electrodes and the gate sidewalls.