Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages
First Claim
Patent Images
1. A row driver circuit contained in an integrated circuit adapted to receive a first external supply voltage and a second external supply voltage, each of the first and second external supply voltages being external to the integrated circuit and the row driver circuit configured to:
- provide during read and write operations the first external supply voltage on an output responsive to the first external supply voltage being greater than a threshold value derived from the second external supply voltage;
generate a plurality of reference voltages that are derived from the second external supply voltage;
generate a boosted voltage from at least one of the plurality of reference voltages and that is greater than the first external supply voltage; and
provide during read and write operations that boosted voltage on the output responsive to the first external supply voltage being less than the threshold value.
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Abstract
A row driver circuit receives a first supply voltage and a second supply voltage. The circuit provides the first supply voltage on an output responsive to the first supply voltage being greater than a threshold value. The circuit generates a boosted voltage that is greater than the first supply voltage and provides that boosted voltage on the output responsive to the first supply voltage being less than the threshold value.
22 Citations
30 Claims
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1. A row driver circuit contained in an integrated circuit adapted to receive a first external supply voltage and a second external supply voltage, each of the first and second external supply voltages being external to the integrated circuit and the row driver circuit configured to:
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provide during read and write operations the first external supply voltage on an output responsive to the first external supply voltage being greater than a threshold value derived from the second external supply voltage; generate a plurality of reference voltages that are derived from the second external supply voltage; generate a boosted voltage from at least one of the plurality of reference voltages and that is greater than the first external supply voltage; and provide during read and write operations that boosted voltage on the output responsive to the first external supply voltage being less than the threshold value. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A row driver circuit contained in an integrated circuit adapted to receive a first external supply voltage and a second external supply voltage, each of the first and second external supply voltages being external to the integrated circuit and the row driver circuit configured to;
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provide during read and write operations the first external supply voltage on an output responsive to a magnitude of the first external supply voltage being greater than a threshold value plus a magnitude of the second external supply voltage; generate a boosted voltage having a magnitude that is greater than the magnitude of the first external supply voltage by an amount that is proportional to a difference between the magnitude of the first external supply voltage and the magnitude of the second external supply voltage; and provide during read and write operations that boosted voltage on the output responsive to the magnitude of the first external supply voltage being less than the threshold value plus the magnitude of the second external supply voltage. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A memory device, comprising:
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a memory-cell array including a plurality of memory cells and a plurality of word lines, each memory cell being coupled to an associated word line; read/write circuitry coupled to a data bus and the memory-cell array; control circuitry coupled between a control bus and the memory-cell array; and address decoder circuitry coupled to an address bus and to the memory-cell array, the address decoder circuitry including a row driver circuit adapted to receive a first external supply voltage and a second external supply voltage supplied to the memory device, and the address decoder circuitry configured to; provide during read and write operations the first external supply voltage on one of the word lines responsive to the first external supply voltage being greater than or equal to a threshold value, generate a plurality of reference voltages that are derived from the second external supply voltage, generate a boosted voltage from at least one of the plurality of reference voltages and that is greater than the first external supply voltage, and provide during read and write operations that boosted voltage on the word line responsive to the first external supply voltage being less than the threshold value. - View Dependent Claims (18, 19, 20)
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21. A computer system, comprising:
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a data input device; a data output device; computer circuitry coupled to the data input and output devices; and a memory device coupled to the computer circuitry, the memory device including, a memory-cell array including a plurality of memory cells and a plurality of word lines, each memory cell being coupled to an associated word line; read/write circuitry coupled to a data bus and the memory-cell array; control circuitry coupled between a control bus and the memory-cell array; and address decoder circuitry coupled to an address bus and to the memory-cell array, the address decoder circuitry including a row driver circuit adapted to receive a first external supply voltage and a second external supply voltage and configured to; provide during read and write operations the first external supply voltage on one of the word lines responsive to the first external supply voltage being greater than or equal to a threshold value, generate a plurality of reference voltages that are derived from the second external supply voltage, generate a boosted voltage from at least one of the plurality of reference voltages and that is greater than the first external supply voltage, and provide during read and write operations that boosted voltage on the word line responsive to the first external supply voltage being less than the threshold value. - View Dependent Claims (22, 23)
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24. A method of generating a boosted voltage in an integrated circuit and accessing stored data in the integrated circuit using the boosted voltage, the method comprising:
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determining whether a magnitude of a first supply voltage external to the integrated circuit is greater than a threshold value plus a magnitude of a second supply voltage external to the integrated circuit; when the magnitude of the first supply voltage external to the integrated circuit is determined to be greater than the threshold value plus the magnitude of the second supply voltage external to the integrated circuit, generating the boosted voltage having a magnitude equal to the magnitude of the first supply voltage external to the integrated circuit; generating a plurality of reference voltages that are derived from the second supply voltage external to the integrated circuit; determining whether the magnitude of the first supply voltage external the integrated circuit is less than the threshold value plus the magnitude of the second supply voltage external to the integrated circuit; and when the magnitude of the first supply voltage external to the integrated circuit is determined to be less than the threshold value plus the magnitude of the second supply voltage external to the integrated circuit, generating the boosted voltage from at least one of the plurality of reference voltages and having a magnitude that is greater than the magnitude of the first supply voltage external to the integrated circuit; and using the boosted voltage during read and write accesses of the stored data in the integrated circuit. - View Dependent Claims (25, 26, 27)
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28. A method of generating a boosted word line voltage to access addressed memory cells in a dynamic random access memory, the memory-cell array including a plurality of word lines and a plurality of access transistors, each access transistor having an associated threshold value, and the method comprising:
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determining whether a magnitude of a pumped supply voltage is greater than or equal to the threshold value plus a magnitude of a lower supply voltage, the pumped supply voltage and the lower supply voltage both being supply voltages generated external to the dynamic access memory; when the magnitude of the pumped supply voltage is greater than or equal to the threshold value plus the magnitude of the lower supply voltage, generating the boosted word line voltage having a magnitude that is equal to-the magnitude of the pumped supply voltage; when the magnitude of the pumped supply voltage is less than the threshold value plus the magnitude of the lower supply voltage, generating the boosted word line voltage having a magnitude that is greater than the magnitude of the pumped supply voltage by an amount that is proportional to a difference between the magnitude of the pumped supply voltage and the magnitude of the lower supply voltage; and during read and write operations, applying the boosted word line voltage on a word line associated with the addressed memory cells. - View Dependent Claims (29, 30)
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Specification