Method and system for creating and programming an adaptive computing engine

• US 7,865,847 B2
• Filed: 01/25/2008
• Issued: 01/04/2011
• Est. Priority Date: 05/13/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L.
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US12/011,340
• Publication Number:
  US 20080134108A1
• Time in Patent Office: 1,075 Days
• Field of Search: 716/1, 716 4- 5, 716 16- 18, 703/2, 703 14- 15, 703 21- 22
• US Class Current: 716/100
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and corresponding method for creating an adaptive computing engine (ACE) includes algorithmic elements, ACE building blocks, and creates a design for heterogeneous nodes to provide appropriate hardware circuit functions that implement the algorithmic elements. Creating the design includes selecting an initial set of the ACE building blocks. The system and corresponding method also optimizes the design by selecting a different set of the ACE building blocks that meets predetermined performance standards for the efficiency of the ACE when performance of the ACE is simulated. The ACE building block preferably belong to one of a plurality of building block types. Preferably, the system and method includes a profiler for providing code to simulate a hardware design that implements the algorithmic elements, for identifying hotspots in the code, and for creating the design based thereon.

Claims

1. A system for creating a configuration for an adaptive computing engine (ACE) having a plurality of heterogeneous nodes having hardware elements, the system comprising:

an algorithmic elements stored in a database;

composite ACE building block types;

means for creating a configuration for at least some of the heterogeneous nodes of the ACE to provide appropriate hardware circuit functions that implement the algorithmic element, by selecting an initial set of the composite ACE building block types required to implement the algorithmic element, and configuring the hardware elements on at least one of the heterogeneous nodes according to the selected initial set of composite ACE building block types; and

means for optimizing the configuration for the heterogeneous nodes by selecting a different set of the composite ACE building block types required to implement the algorithmic element that meets predetermined performance standards for efficiency of the ACE when performance of the ACE is simulated.

2. The system of claim 1, wherein the composite ACE building block types belong to at least one of a plurality of composite ACE building blocks types including linear computation block types, finite state machine block types, field programmable gate array block types, processor block types, and memory block types.

3. The system of claim 2, wherein the linear computation block types are selected from the group consisting of:

multipliers, adders, double adders, multiply double accumulators, radix 2, discrete cosine transform (DCT), finite impulse response (FIR), infinite impulse response (IIR), Fast Fourier Transform (FFT), square root, and divides.

4. The system of claim 1, wherein the means for creating a design further includes a profiler that comprises:

means for providing code to simulate a hardware design that implements the algorithmic elements; and

means for identifying one or more hot spots in the code, wherein the identified hot spots are those areas of code requiring high power and/or high data movement; and

wherein the means for creating a design selects the initial set of the composite ACE building block types based on the identified hot spots.

5. The system of claim 4, wherein each hot spot comprises a computational hot spot or a data movement hot spot.

6. The system of claim 5, wherein the means for creating a design uses each data movement hot spot to restrict high data movements to a minimum physical distance in the ACE.

7. The system of claim 1, wherein the hardware elements of the heterogeneous nodes are coupled with each other by a configurable and reconfigurable interconnection network.

8. The system of claim 7, wherein the heterogeneous nodes are configurable and reconfigurable to provide appropriate hardware circuit functions for implementing the algorithmic elements by configuring and reconfiguring the reconfigurable interconnection network coupling the hardware elements.

9. The system of claim 1, wherein the composite ACE building block types are stored in a database.

10. The system of claim 1, wherein the different set of composite ACE building block types that meets the predetermined performance standards for efficiency of the ACE when performance of the ACE is simulated is stored in a database.

11. The method of claim 1, wherein the ACE is reconfigured to perform a different algorithmic element via selecting another set of composite ACE building block types and configuring the hardware elements one at least one of the heterogeneous nodes according to the another set of composite ACE building block types.

12. A method for creating a configuration for an adaptive computing engine (ACE) having a plurality of heterogeneous nodes, each heterogeneous node including a plurality of hardware elements, the method comprising:

providing an algorithmic elements;

providing composite ACE building block types;

creating a configuration for at least some of the heterogeneous nodes of the ACE to provide appropriate hardware circuit functions that implement the algorithmic elements comprising;

selecting an initial set of the composite ACE building block types required to implement the algorithmic element;

configuring the hardware elements on at least one of the heterogeneous nodes according to the selected initial set of composite ACE building block types; and

optimizing the design for the heterogeneous nodes comprising;

simulating performance of the ACE;

selecting a different set of the composite building block types required to perform the algorithmic element that meets predetermined performance standards for efficiency of the ACE when performance of the ACE is simulated by a computer.

13. The method of claim 12, wherein the composite building block types belong to at least one of a plurality of composite ACE building blocks types including linear computation block types, finite state machine block types, field programmable gate array block types, processor block types, and memory block types.

14. The method of claim 13, wherein the linear computation block types are selected from the group consisting of:

multipliers, adders, double adders, multiply double accumulators, radix 2, discrete cosine transform (DCT), finite impulse response (FIR) infinite impulse response (IIR), Fast Fourier Transform (FFT), square root, and divides.

15. The method of claim 12, wherein the creating a design further includes profiling using a profiler, wherein the profiling comprises:

providing code to simulate a hardware design that implements the algorithmic elements; and

identifying one or more hot spots in the code, wherein the identified hot spots are those areas of code requiring high power and/or high data movement; and

wherein the creating a design further comprises selecting the initial set of the composite ACE building block types based on the identified hot spots.

16. The method of claim 15, wherein each hot spot comprises a computational hot spot or a data movement hot spot.

17. The method of claim 16, wherein the creating a design uses each data movement hot spot to restrict high data movements to a minimum physical distance in the ACE.

18. The method of claim 12, wherein the hardware elements of the heterogeneous nodes of the ACE are coupled with each other by a configurable and reconfigurable interconnection network.

19. The method of claim 18, wherein the heterogeneous nodes of the ACE are configurable and reconfigurable to provide appropriate hardware circuit functions for implementing the algorithmic elements by configuring and reconfiguring the interconnection network and the hardware elements.

20. The method of claim 12, wherein the composite ACE building blocks types are stored in a database.

21. The method of claim 12, further comprising storing in a database the different set of composite ACE building block types that meets the predetermined performance standards for efficiency of the ACE when performance of the ACE is simulated.