Methods of manufacturing semiconductor devices

• US 7,867,867 B2
• Filed: 11/07/2006
• Issued: 01/11/2011
• Est. Priority Date: 11/07/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Andrew-tae, Shin, Dong-suk, Jeong, Yong-kuk
• Primary Examiner(s): Kebede; Brook
• Application Number:
  US11/593,898
• Publication Number:
  US 20070105297A1
• Time in Patent Office: 1,526 Days
• Field of Search: 438/199, 438/200, 438/308, 438/142, 438/197, 257/E27.046, 257/E27.108, 257/E21.632
• US Class Current: 438/308
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer on the NMOS transistor; and

increasing a tensile stress in a channel region of the NMOS transistor by dehydrogenating the first interlayer dielectric layer.

2. The method of claim 1, wherein dehydrogenating the first interlayer dielectric layer increases a tensile stress of the first interlayer dielectric layer and increases a compressive stress in a source/drain region of the NMOS transistor.

3. The method of claim 1, wherein dehydrogenating the first interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere.

4. The method claim 3, wherein the dehydrogenation gas comprises N₂, O₂, O₃, N₂O, H₂, and/or D₂.

5. The method of claim 1, wherein the first interlayer dielectric layer has a tensile stress of at least about 200 MPa after dehydrogenization.

6. The method of claim 1, wherein the first interlayer dielectric layer comprises O₃-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, and/or TOSZ.

7. The method of claim 1, further comprising forming contacts connected to the NMOS transistor in the first interlayer dielectric layer after forming the first interlayer dielectric layer.

8. The method of claim 1, further comprising forming a liner layer having a tensile stress directly on source/drain regions of the NMOS transistor before forming the first interlayer dielectric layer.

9. The method of claim 1, wherein:

forming the NMOS transistor on the semiconductor substrate comprises forming the NMOS transistor and a PMOS transistor on the semiconductor substrate; and

forming the first interlayer dielectric layer on the NMOS transistor comprises forming the first interlayer dielectric layer on the NMOS transistor and on the PMOS transistor.

10. The method of claim 9, further comprising implanting germanium and/or nitrogen ions into a portion of the first interlayer dielectric layer formed on the PMOS transistor after dehydrogenating the first interlayer dielectric layer.

11. The method of claim 9, further comprising forming a mask pattern on a portion of the first interlayer dielectric layer formed on the PMOS transistor before dehydrogenating the first interlayer dielectric layer.

13. The method of claim 1, further comprising forming a capping layer on the first interlayer dielectric layer after dehydrogenating the first interlayer dielectric layer, wherein the capping layer obstructs or hinders moisture and/or external ions from penetrating into the first interlayer dielectric layer.

14. The method of claim 13, wherein forming the capping layer comprises forming the capping layer in an in-situ process after dehydrogenating the first interlayer dielectric layer.

12. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer on the NMOS transistor;

dehydrogenating the first interlayer dielectric layer; and

forming a second interlayer dielectric layer on the first interlayer dielectric layer after dehydrogenating the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a stress smaller than a stress of the first interlayer dielectric layer after dehydrogenating the first interlayer dielectric layer.

15. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer on the NMOS transistor;

dehydrogenating the first interlayer dielectric layer; and

forming a liner layer having a tensile stress on the NMOS transistor before forming the first interlayer dielectric layer;

wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the first interlayer dielectric layer is represented by t2, and wherein t2/t1≧

1.14.

16. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer on the NMOS transistor;

dehydrogenating the first interlayer dielectric layer;

after dehydrogenating the first interlayer dielectric layer,

forming an additional interlayer dielectric layer, which has a stress, on the first interlayer dielectric layer; and

dehydrogenating the additional interlayer dielectric layer;

wherein forming the additional interlayer dielectric layer and dehydrogenating the additional interlayer dielectric layer are repeated one or more times.

17. The method of claim 16, wherein dehydrogenating the additional interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or a thermal treatment on the additional interlayer dielectric layer in a dehydrogenation gas atmosphere.

18. The method of claim 17, further comprising forming a liner layer having a tensile stress on the NMOS transistor before forming the first interlayer dielectric layer.

19. The method of claim 18, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer, the dehydrogenated first interlayer dielectric layer, and the dehydrogenated additional interlayer dielectric layer is represented by t3, and wherein t3/t1≧

1.14.

20. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer, which includes an O₃-TEOS layer having a tensile stress, on the NMOS transistor; and

dehydrogenating the first interlayer dielectric layer.

21. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere.

22. The method claim 21, wherein the dehydrogenation gas comprises N₂, O₂, O₃, N₂O, H₂, and/or D₂.

23. The method of claim 20, wherein the first interlayer dielectric layer has a tensile stress of 200 MPa or more following dehydrogenization.

24. The method of claim 20, further comprising, after forming the first interlayer dielectric layer, forming contacts connected to the NMOS transistor in the first interlayer dielectric layer.

25. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, the method further comprising forming a second interlayer dielectric layer on the dehydrogenated first interlayer dielectric layer, wherein the second interlayer dielectric layer has a stress smaller than a stress of the dehydrogenated first interlayer dielectric layer.

26. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, the method further comprising forming a capping layer on the dehydrogenated first interlayer dielectric layer, wherein the capping layer is configured to obstruct or hinder moisture and/or external ions from penetrating into the dehydrogenated first interlayer dielectric layer.

27. The method of claim 26, wherein forming the capping layer comprises forming the capping layer in an in-situ process after dehydrogenating the first interlayer dielectric layer.

28. The method of claim 20, further comprising, before forming the first interlayer dielectric layer, forming a liner layer having a tensile stress on the NMOS transistor.

29. The method of claim 27, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the dehydrogenated first interlayer dielectric layer is represented by t2, and wherein t2/t1≧

1.14.

30. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, the method further comprising:

forming an additional interlayer dielectric layer having a tensile stress on the dehydrogenated first interlayer dielectric layer; and

dehydrogenating the additional interlayer dielectric layer;

wherein forming the additional interlayer dielectric layer and dehydrogenating the additional interlayer dielectric layer are repeated one or more times.

31. The method of claim 30, wherein dehydrogenating the additional interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or thermal treatment on the additional interlayer dielectric layer in a dehydrogenation gas atmosphere.

32. The method of claim 31, further comprising, before forming the first interlayer dielectric layer, forming a liner layer having a tensile stress on the NMOS transistor.

33. The method of claim 32, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, wherein dehydrogenating the additional interlayer dielectric layer comprises forming a dehydrogenated additional interlayer dielectric layer, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer, the dehydrogenated first interlayer dielectric layer, and the dehydrogenated additional interlayer dielectric layer is represented by t3, and wherein t3/t1≧

1.14.

34. The method of claim 20, wherein:

forming the NMOS transistor on the semiconductor substrate comprises forming the NMOS transistor and a PMOS transistor on the semiconductor substrate; and

forming the first interlayer dielectric layer on the NMOS transistor comprises forming the first interlayer dielectric layer on the NMOS transistor and the PMOS transistor.

35. The method of claim 34, further comprising implanting germanium and/or nitrogen ions into a portion of the first interlayer dielectric layer formed on the PMOS transistor after dehydrogenating the first interlayer dielectric layer.

36. The method of claim 34, further comprising forming a mask pattern on a portion of the first interlayer dielectric layer formed on the PMOS transistor before dehydrogenating the first interlayer dielectric layer.