Digital phase-locked loop with two-point modulation and adaptive delay matching

• US 7,868,672 B2
• Filed: 12/09/2008
• Issued: 01/11/2011
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Geng, Jifeng, Ballantyne, Gary John, Filipovic, Daniel F.
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Houston; Adam D
• Application Number:
  US12/330,885
• Publication Number:
  US 20100141313A1
• Time in Patent Office: 763 Days
• Field of Search: 327/149, 327/158
• US Class Current: 327/158
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0966 modulating the reference clock

Abstract

A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.

Claims

1. An apparatus comprising:

a digital phase-locked loop (DPLL) configured to perform two-point modulation via first and second modulation paths and to adaptively adjust delay of the first modulation path to match delay of the second modulation path.

2. The apparatus of claim 1, wherein the DPLL comprises

an adaptive delay unit configured to provide a variable delay for the first modulation path.

3. The apparatus of claim 2, wherein the adaptive delay unit comprises

a delay computation unit configured to determine the variable delay based on a modulating signal applied to the first and second modulation paths.

4. The apparatus of claim 3, wherein the delay computation unit determines the variable delay based further on a phase error signal in the DPLL.

5. The apparatus of claim 4, wherein the delay computation unit determines a delay update value based on the phase error signal, a sign of the modulating signal, and an adaptation step size, and updates the variable delay with the delay update value.

6. The apparatus of claim 2, wherein the adaptive delay unit determines the variable delay in accordance with a least mean square (LMS) algorithm, a least square (LS) algorithm, or a minimum mean square error (MMSE) algorithm.

7. The apparatus of claim 2, wherein the adaptive delay unit comprises

an interpolator configured to provide a fractional portion of the variable delay, the fractional portion being between minus one sample period and plus one sample period.

8. The apparatus of claim 7, wherein the interpolator performs linear interpolation based on a current sample and a prior sample for a positive fractional delay and based on the current sample and a future sample for a negative fractional delay.

9. The apparatus of claim 2, wherein the adaptive delay unit comprises

a programmable delay unit configured to provide an integer portion of the variable delay, the integer portion comprising an integer number of sample periods.

10. The apparatus of claim 1, wherein the first modulation path is a highpass modulation path and the second modulation path is a lowpass modulation path, and wherein the DPLL adaptively adjusts the delay of the highpass modulation path.

11. The apparatus of claim 1, wherein the first modulation path is a lowpass modulation path and the second modulation path is a highpass modulation path, and wherein the DPLL adaptively adjusts the delay of the lowpass modulation path.

12. The apparatus of claim 1, wherein one of the first and second modulation paths is a highpass modulation path, and wherein the other one of the first and second modulation paths is a lowpass modulation path.

13. The apparatus of claim 12, wherein the DPLL comprises

an adaptive scaling unit configured to provide a variable gain for the highpass modulation path to match gain of the lowpass modulation path.

14. The apparatus of claim 13, wherein the adaptive scaling unit determines the variable gain based on a modulating signal applied to the highpass and lowpass modulation paths and a phase error signal in the DPLL.

15. The apparatus of claim 12, wherein the highpass modulation path comprises a scaling unit configured to scale a modulating signal and provide a scaled modulating signal, and wherein the lowpass modulation path comprises a delta-sigma modulator configured to receive the modulating signal and provide an output signal used to vary a frequency divider factor in the DPLL.

16. The apparatus of claim 12, wherein the highpass modulation path comprises a scaling unit configured to scale a modulating signal and provide a scaled modulating signal, and wherein the lowpass modulation path comprises an accumulator configured to accumulate the modulating signal and provide a modulating phase signal.

17. The apparatus of claim 1, wherein the apparatus is an integrated circuit.

18. The apparatus of claim 1, wherein the apparatus is a wireless communication device.

19. An apparatus comprising:

a processor configured to perform two-point modulation via first and second modulation paths of a digital phase-locked loop (DPLL) and to adaptively adjust delay of the first modulation path to match delay of the second modulation path.

20. A method comprising:

applying a modulating signal to a first modulation path of a digital phase-locked loop (DPLL) supporting two-point modulation;

applying the modulating signal to a second modulation path of the DPLL; and

adaptively adjusting delay of the first modulation path to match delay of the second modulation path.

21. The method of claim 20, wherein the adaptively adjusting delay of the first modulation path comprises

determining a variable delay for the first modulation path based on the modulating signal and a phase error signal in the DPLL.

22. The method of claim 21, wherein the determining the variable delay comprises

determining a delay update value based on the phase error signal, a sign of the modulating signal, and an adaptation step size, and

updating the variable delay with the delay update value.

23. The method of claim 21, wherein the adaptively adjusting delay of the first modulation path comprises

providing a fractional portion of the variable delay with interpolation, the fractional portion being between minus one sample period and plus one sample period.

24. The method of claim 21, wherein the adaptively adjusting delay of the first modulation path comprises

providing an integer portion of the variable delay with a programmable delay unit, the integer portion comprising an integer number of sample periods.

25. The method of claim 20, further comprising:

adaptively adjusting gain of a highpass modulation path to match gain of a lowpass modulation path, wherein one of the first and second modulation paths is the highpass modulation path, and wherein the other one of the first and second modulation paths is the lowpass modulation path.

26. An apparatus comprising:

means for applying a modulating signal to a first modulation path of a digital phase-locked loop (DPLL) supporting two-point modulation;

means for applying the modulating signal to a second modulation path of the DPLL; and

means for adaptively adjusting delay of the first modulation path to match delay of the second modulation path.

27. The apparatus of claim 26, wherein the means for adaptively adjusting delay of the first modulation path comprises

means for determining a variable delay for the first modulation path based on the modulating signal and a phase error signal in the DPLL.

28. The apparatus of claim 27, wherein the means for adaptively adjusting delay of the first modulation path comprises

means for providing a fractional portion of the variable delay with interpolation, the fractional portion being between minus one sample period and plus one sample period.

29. The apparatus of claim 26, further comprising:

means for adaptively adjusting gain of a highpass modulation path to match gain of a lowpass modulation path, wherein one of the first and second modulation paths is the highpass modulation path, and wherein the other one of the first and second modulation paths is the lowpass modulation path.

30. A non-transitory computer-readable medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations comprising:

applying a modulating signal to a first modulation path of a digital phase-locked loop (DPLL) supporting two-point modulation;

applying the modulating signal to a second modulation path of the DPLL; and

adaptively adjusting delay of the first modulation path to match delay of the second modulation path.

31. The computer-readable medium of claim 30, wherein the stored processor-executable software instructions are configured to cause a processor to perform further operations comprising:

determining a variable delay for the first modulation path based on the modulating signal and a phase error signal in the DPLL.

32. The computer-readable medium of claim 31, wherein the stored processor-executable software instructions are configured to cause a processor to perform further operations comprising:

providing a fractional portion of the variable delay with interpolation, the fractional portion being between minus one sample period and plus one sample period.

33. The computer-readable medium of claim 30, wherein the stored processor-executable software instructions are configured to cause a processor to perform further operations comprising:

adaptively adjusting gain of a highpass modulation path to match gain of a lowpass modulation path, wherein one of the first and second modulation paths is the highpass modulation path, and wherein the other one of the first and second modulation paths is the lowpass modulation path.