Method and structure to support system resource access of a serial device implementating a lite-weight protocol

• US 7,870,313 B2
• Filed: 02/27/2007
• Issued: 01/11/2011
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Chi-Lie, Mo, Jason Z., Nguyen, Calvin
• Primary Examiner(s): Shin; Christopher B
• Application Number:
  US11/679,817
• Publication Number:
  US 20080205422A1
• Time in Patent Office: 1,414 Days
• Field of Search: 710 52- 56, 710 22- 28, 710105-106, 710305-310, 370412-419, 370/389
• US Class Current: 710/52
• CPC Class Codes: H04L 47/2483 involving identification of individual flows
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.

Claims

1. A serial buffer comprising:

a serial interface that receives both data packets and priority packets;

a data processor coupled to receive the data packets, but not the priority packets, from the serial interface, wherein the data processor transfers the data packets to one or more queues; and

a priority packet processor coupled to receive the priority packets, but not the data packets, from the serial interface, wherein the priority packet processor accesses on-chip resources of the serial buffer in response to the priority packets.

2. The serial buffer of claim 1, wherein each of the priority packets includes a control field identifying the start of a priority packet.

3. The serial buffer of claim 1, wherein the priority packets received on the serial interface are sequentially numbered using a packet identification field, which is included in each of the priority packets.

4. The serial buffer of claim 1, wherein the priority packet processor includes a decoder configured to decode commands embedded in the priority packets, thereby identifying different types of access operations specified by the priority packets.

5. The serial buffer of claim 4, wherein the priority packet processor further includes an address register configured to store address information embedded in the priority packets, wherein the address information identifies on-chip resources of the serial buffer to be accessed.

6. The serial buffer of claim 5, wherein the priority packet processor further includes a data register configured to store data embedded in the priority packets, wherein the data is transferred from the data register to the on-chip resources identified by the address information stored in the address buffer.

7. The serial buffer of claim 4, wherein the priority packet processor is configured to implement a configuration read access to an on-chip register of the serial buffer in response to a configuration read command embedded in a priority packet.

8. The serial buffer of claim 7, wherein the priority packet processor further includes a response generator configured to provide a priority packet containing data read from the on-chip register of the serial buffer in response to the configuration read command.

9. The serial buffer of claim 4, wherein the priority packet processor is configured to implement a write access to an on-chip register of the serial buffer in response to a configuration write command embedded in a priority packet.

10. The serial buffer of claim 4, wherein the priority packet processor is configured to implement a read access to one of the one or more queues in response to a read request command embedded in a priority packet.

11. The serial buffer of claim 10, wherein the priority packet processor further includes a register configured to store queue address information embedded in the priority packets, wherein the queue address information identifies a queue to be accessed in response to a read request command.

12. The serial buffer of claim 1, wherein the priority packet processor further includes a doorbell generator configured to receive a doorbell request from flag control logic of the serial buffer, and in response, provide a priority packet containing a flag address and flag data associated with the flag address.

13. The serial buffer of claim 1, wherein the on-chip resources of the serial buffer comprises one or more configuration registers of the serial buffer.

14. The serial buffer of claim 1, wherein the data processor operates in parallel with the priority packet processor.

15. The serial buffer of claim 14, wherein the priority packet processor accesses the on-chip resources of the serial buffer without interruption from the data processor.

16. A method of operating a serial buffer comprising:

receiving both data packets and priority packets on a serial interface of the serial buffer;

routing the data packets received on the serial interface to a data processor of the serial buffer;

using the data processor to transfer the data packets to one or more queues;

routing the priority packets received on the serial interface to a priority packet processor; and

using the priority packet processor to access on-chip resources of the serial buffer in response to the priority packets.

17. The method of claim 16, further comprising identifying the start of each of the priority packets in response to a control field present in each of the priority packets.

18. The method of claim 16, further comprising determining the integrity of the priority packets received on the serial interface by detecting whether the priority packets received on the serial interface are sequentially numbered.

19. The method of claim 16, further comprising decoding commands embedded in the priority packets, thereby identifying different types of access operations specified by the priority packets.

20. The method of claim 19, further comprising storing address information embedded in the priority packets, wherein the address information identifies on-chip resources of the serial buffer to be accessed.

21. The method of claim 20, further comprising storing data embedded in the priority packets, wherein the data is written to the on-chip resources of the serial buffer identified by the address information.

22. The method of claim 19, further comprising reading configuration data from an on-chip register of the serial buffer in response to one type of access operation specified by the priority packets.

23. The method of claim 22, further comprising providing a priority packet containing configuration data read from the on-chip register of the serial buffer.

24. The method of claim 19, further comprising writing configuration data to an on-chip register of the serial buffer in response to one type of access operation specified by the priority packets.

25. The method of claim 19, further comprising using the priority packet processor to retrieve data from a queue of the one or more queues in response to one type of access operation specified by the priority packets.

26. The method of claim 25, further comprising selecting the queue in response to a queue address embedded in the priority packets.

27. The method of claim 16, further comprising:

receiving a doorbell request from flag control logic of the serial buffer; and

, in response

providing a priority packet containing a flag address and flag data associated with the flag address.

28. The method of claim 16, further comprising operating the data processor in parallel with the priority packet processor, wherein the priority packet processor accesses the on-chip resources of the serial buffer without interruption from the data processor.