Stacked structures and methods of fabricating stacked structures

• US 7,879,711 B2
• Filed: 11/28/2006
• Issued: 02/01/2011
• Est. Priority Date: 11/28/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Weng-Jin, Yu, Chen-Hua, Wang, Jean, Chiou, Wen-Chih
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Parker; John M
• Application Number:
  US11/563,973
• Publication Number:
  US 20080124845A1
• Time in Patent Office: 1,526 Days
• Field of Search: 438/455, 438/586, 438/598, 438/618, 438/622, 438/926, 257/E23.145
• US Class Current: 438/598
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14179 Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/17517 including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29013 being rectangular or square
• CPC Class Codes: H01L 2224/29035 covering only the peripheral area of the surface to be connected
• CPC Class Codes: H01L 2224/29075 Plural core members
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/29184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/29186 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/3003 : Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/30155 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/73103 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/049 : Nitrides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10S 438/926 : Dummy metallization

Abstract

A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

Claims

1. A method of forming a semiconductor device, comprising the steps of:

forming at least one transistor gate over a first substrate and at least one first conductive structure within the first substrate;

forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer comprising at least one contact structure formed therein and making electrical contact with the transistor gate and at least one second conductive structure and making electric contact with the first conductive structure;

forming a first passivation layer over the ILD layer, the first passivation layer comprising at least one first pad structure formed therein, wherein the first pad structure makes electrical contact with the second conductive structure;

bonding the first substrate with a second substrate;

removing at least a portion of the first conductive structure; and

forming a second passivation layer over a bottom surface of the first substrate, the second passivation layer comprising at least one second pad structure formed therein, wherein the second pad structure makes electrical contact with the first conductive structure.

2. The method of claim 1, further comprising:

thinning the bottom surface of the first substrate to expose at least one dummy structure disposed within the first substrate; and

removing a portion of the at least one dummy structure from the first substrate to provide an opening within the first substrate and to expose a surface of the at least one first conductive structure.

3. The method of claim 2, further comprising:

filling the opening within the first substrate with a conductive material.

4. The method of claim 1, further comprising:

thinning the first substrate to expose at least one dummy structure disposed within the first substrate;

removing the dummy structure from the first substrate to provide an opening having sidewalls;

forming a dielectric liner on the sidewalls of the opening; and

filling the opening within the first substrate with a conductive material.

5. The method of claim 1, further comprising bonding a third substrate to the first substrate.

6. The method of claim 1, further comprising:

forming at least one opening in the first substrate; and

depositing a dielectric material within the at least one opening to create a dummy structure; and

removing a portion of the dummy structure such that an upper surface of the dummy structure is substantially planar with an upper surface of the first substrate.

7. A method, comprising:

forming a dummy structure in a first substrate;

forming a transistor gate over a first surface of the first substrate;

forming an interlayer dielectric (ILD) layer over a surface of the transistor gate and the dummy structure, the ILD layer including a contact structure formed therein, the contact structure coupled to the transistor gate;

forming a first conductive structure in the interlayer dielectric, the first conductive structure coupled to the contact structure;

forming a first passivation layer over an intermetal dielectric (IMD) layer formed over the ILD layer, the passivation layer including a conductive pad coupled to the first conductive structure in the ILD layer;

bonding a second substrate to the first substrate;

removing a portion of the dummy structure in the first substrate to expose a surface of the first conductive structure;

filling an opening created by the removal of the portion of the dummy structure with a conductive material; and

forming a second passivation layer over the second surface of the first substrate, the second passivation layer including a second pad structure formed therein, the second pad structure making electrical contact with the first conductive structure through the conductive material.

8. The method of claim 7, further comprising thinning the first substrate prior to removing the portion of the dummy structure.

9. The method of claim 7, wherein the dummy structure is completely removed from the first substrate, the method further comprising covering a sidewall of the opening created by the removal of the dummy structure with a dielectric material prior to filling the opening with the conductive material.

10. The method of claim 7, wherein the second pad structure is directly disposed over the conductive material disposed in the opening created by the removal of the portion of the dummy structure, the method further comprising bonding a third substrate to the first substrate.

11. A method, comprising:

forming an interlayer dielectric (ILD) layer over a gate of a transistor formed over a first surface of a first substrate, the ILD layer including a first conductive structure formed therein that makes electrical contact with the transistor gate and a first contact structure disposed within the ILD layer;

forming a first passivation layer over the ILD layer, the first passivation layer including a first pad structure formed therein, the first pad structure making electrical contact with the first conductive structure;

bonding the first substrate with a second substrate;

thinning the first substrate; and

forming a second passivation layer over a second surface of the first substrate, the second passivation layer including a second pad structure formed therein, the second pad structure making electrical contact with the first conductive structure.

12. The method of claim 11, further comprising:

forming a first opening in the first substrate;

depositing a dielectric material within the first opening to create a dummy structure; and

removing a first portion of the dummy structure such that an upper surface of the dummy structure is substantially planar with the first surface of the first substrate.

13. The method of claim 12, further comprising:

removing the dummy structure from the first substrate to create a second opening and to expose a surface of the first conductive structure; and

filling the second opening with a conductive material, the conductive material contacting the first conductive structure and providing the electrical contact to the second pad structure.

14. The method of claim 13, further comprising bonding a third substrate to the second surface of the first substrate.

15. The method of claim 14, wherein the third substrate includes a third pad structure electrically connected to the second pad structure.

16. The method of claim 12, further comprising:

removing a second portion of the dummy structure to create a second opening having sidewalls and to expose a surface of the first conductive structure;

forming a dielectric material over the sidewalls of the second opening; and

filling a remainder of the second opening with a conductive material, the conductive material contacting the first conductive structure and providing the electrical contact to the second pad structure.

17. The method of claim 16, further comprising bonding a third substrate to the second surface of the first substrate.

18. The method of claim 17, wherein the third substrate includes a third pad structure electrically connected to the second pad structure.

19. The method of claim 11, further comprising:

forming an intermetal dielectric (IMD) layer over a surface of the ILD layer before the first passivation layer is formed over the IMD layer, the IMD layer including at least one metal containing structure to electrically connect the first conductive structure in the ILD layer to the first pad structure in the first passivation layer.

20. The method of claim 19, wherein the IMD layer includes a plurality of dielectric and metal containing layers.