Post passivation interconnection schemes on top of the IC chips
First Claim
1. An integrated circuit chip comprising:
- a silicon substrate;
a first internal circuit in and on said silicon substrate;
a second internal circuit in and on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a layer of nitrogen-containing compound;
a first via in said passivation layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said passivation layer;
a second via in said passivation layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; and
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a thickness between 2 and 100 micrometers, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer.
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Accused Products
Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
103 Citations
28 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate; a first internal circuit in and on said silicon substrate; a second internal circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a layer of nitrogen-containing compound; a first via in said passivation layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said passivation layer; a second via in said passivation layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a thickness between 2 and 100 micrometers, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit chip comprising:
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a silicon substrate; an internal circuit in and on said silicon substrate; an ESD circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said ESD circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a layer of a nitrogen-containing compound; a first via in said passivation layer, wherein said first via is connected to said internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said passivation layer; a second via in said passivation layer, wherein said second via is connected to said ESD circuit through said second interconnecting structure; and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a thickness between 2 and 100 micrometers, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer. - View Dependent Claims (7, 8, 9, 10)
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11. An integrated circuit chip comprising:
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a silicon substrate; a first internal circuit in and on said silicon substrate; a second internal circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; an insulating layer over said dielectric layer; a first via in said insulating layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer; a second via in said insulating layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; and a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer. - View Dependent Claims (12, 13, 14, 15)
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16. An integrated circuit chip comprising:
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a silicon substrate; an internal circuit in and on said silicon substrate; an ESD circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said internal circuit, and wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said ESD circuit; an insulating layer over said dielectric layer; a first via in said insulating layer, wherein said first via is connected to said internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer; a second via in said insulating layer, wherein said second via is connected to said ESD circuit through said second interconnecting structure; and a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer. - View Dependent Claims (17, 18, 19, 20)
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21. An integrated circuit chip comprising:
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a silicon substrate; a first internal circuit in and on said silicon substrate; a second internal circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, and wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; an insulating layer over said dielectric layer; a first via in said insulating layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer; a second via in said insulating layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer and a metal layer over said second adhesion layer; and a polymer layer over said insulating layer, wherein said polymer layer comprises a portion over said third interconnecting structure. - View Dependent Claims (22, 23, 24)
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25. An integrated circuit chip comprising:
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a silicon substrate; an ESD circuit in and on said silicon substrate; an internal circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said internal circuit, and wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said ESD circuit; an insulating layer over said dielectric layer; a first via in said insulating layer, wherein said first via is connected to said internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said insulating layer; a second via in said insulating layer, wherein said second via is connected to said ESD circuit through said second interconnecting structure; a third interconnecting structure over said insulating layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said third interconnecting structure comprises a second adhesion layer and a metal layer over said second adhesion layer; and a polymer layer over said insulating layer, wherein said polymer layer comprises a portion over said third interconnecting structure. - View Dependent Claims (26, 27, 28)
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Specification