Methods and apparatus for providing simultaneous software/hardware cache fill

• US 7,886,112 B2
• Filed: 06/01/2006
• Issued: 02/08/2011
• Est. Priority Date: 05/24/2006
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Ohtsuka, Katsushi
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US11/444,803
• Publication Number:
  US 20070277000A1
• Time in Patent Office: 1,713 Days
• Field of Search: 711/3, 711/122, 711/133, 711/137, 711/144, 711/145, 711202-209, 711/118
• US Class Current: 711/137
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/654 Look-ahead translation

Abstract

Methods and apparatus provide a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; provide a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refill the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.

Claims

1. A method, comprising:

providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system;

providing a software implemented cache refill function operable to pre-load the at least one address translation table cache prior to a cache miss;

permitting application software, running on the processing system, to call operating system software of the processing system to;

(i) control the hardware implemented cache refill circuit and the software implemented cache refill function to operate simultaneously in managing the at least one address translation table cache; and

(ii) determine which of the hardware implemented cache refill circuit or the software implemented cache refill function is to operate, and which is not to operate, in managing the at least one address translation table cache.

2. The method of claim 1, wherein the pre-loading step reserves one or more cache lines of the at least one address translation table cache and one or more associated physical memory locations, addressed by the physical addresses, in a memory of the processing system.

3. The method of claim 1, wherein the pre-loading step includes locking one or more of the cache lines of the at least one address translation table cache against a refill by the hardware implemented cache refill circuit.

4. The method of claim 3, further comprising, after a cache miss:

searching, with the hardware implemented cache refill circuit, the cache lines of the at least one address translation table cache for one or more invalid and/or unlocked cache lines; and

refilling, with the hardware implemented cache refill circuit, the one or more invalid and/or unlocked cache lines.

5. The method of claim 4, further comprising:

issuing an interrupt for a fault notification when there are no available invalid and/or unlocked cache lines.

6. An address translation circuit, comprising:

a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a memory space; and

a software implemented cache refill function also for managing the at least one address translation table cache, wherein

the hardware implemented cache refill circuit and the software implemented cache refill function are operable to simultaneously refill the at least one address translation table cache, and

application software, running on the processing system, calls operating system software of the processing system to;

(i) control the hardware implemented cache refill circuit and the software implemented cache refill function, to operate simultaneously in managing the at least one address translation table cache; and

(ii) determine which of the hardware implemented cache refill circuit or the software implemented cache refill function is to operate, and which is not to operate, in managing the at least one address translation table cache.

7. The address translation circuit of claim 6, wherein:

the at least one address translation table cache includes at least one segment table cache, each cache line of the segment table cache representing a different segment of the memory space of the processing system; and

the at least one address translation table cache includes at least one page table cache, each entry in the page table cache including at least a portion of a physical address in the memory space and belonging to a group of entries representing a page in a given segment of the memory space.

8. The address translation circuit of claim 7, wherein the software implemented cache refill function is operable to reserve one or more cache lines of the at least one address translation table cache and one or more associated physical memory locations, addressed by the physical addresses, in the memory space.

9. The address translation circuit of claim 8, wherein the software implemented cache refill function is operable to lock the one or more of the cache lines against a refill by the hardware implemented cache refill circuit after a cache miss.

10. A method, comprising:

providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system;

providing a software implemented cache refill function also for managing the at least one address translation table cache;

permitting application software, running on the processing system, to call operating system software of the processing system to determine which of the hardware implemented cache refill circuit or the software implemented cache refill function is to operate, and which is not to operate, in managing the at least one address translation table cache;

refilling the at least one address translation table cache using one of the hardware implemented cache refill circuit and the software implemented cache refill function determined by the application or operating system software;

permitting application software, running on the processing system, to call operating system software of the processing system, which controls the hardware implemented cache refill circuit and the software implemented cache refill function, to operate simultaneously in managing the at least one address translation table cache; and

refilling the at least one address translation table cache simultaneously using the hardware implemented cache refill circuit and the software implemented cache refill function.

11. The method of claim 10, wherein the software implemented cache refill function operates to pre-load the at least one address translation table cache prior to a cache miss.

12. The method of claim 11, wherein:

the at least one address translation table cache includes at least one segment table cache, each cache line of the segment table cache representing a different segment of a memory of the processing system; and

the at least one address translation table cache includes at least one page table cache, each entry in the page table cache including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory.

13. The method of claim 12, further comprising:

permitting the software implemented cache refill function to reserve one or more cache lines of the at least one address translation table cache and one or more associated physical memory locations, addressed by the physical addresses, in the memory of the processing system.

14. The method of claim 13, further comprising:

permitting the software implemented cache refill function to lock the one or more of the cache lines against a refill by the hardware implemented cache refill circuit.

15. The method of claim 12, further comprising:

adding a base address to the external address to produce at least a portion of an intermediate address;

using a first portion of the intermediate address as a pointer to select one of the cache lines of the segment table cache;

using at least a portion of the selected cache line of the segment table cache as a reference to a plurality of cache lines of the page table cache; and

using another portion of the intermediate address as a pointer to one of the referenced entries in the page table cache to obtain an at least partially translated physical address into the memory for the external address.

16. The method of claim 15, wherein one or more cache lines of the segment table cache include at least one of:

one or more bits indicative of whether the given cache line is valid;

one or more bits indicative of a page number of the page table cache;

one or more bits indicative of a page size of the page table cache; and

one or more bits providing the reference to the plurality of cache lines of the page table cache.

17. The method of claim 15, wherein one or more cache lines of the page table cache include at least one of:

one or more bits indicative of whether the given cache line is valid;

one or more bits indicative of whether the given cache line has been locked, prior to a cache miss, by the software implemented cache refill function against a refill by the hardware implemented cache refill circuit; and

one or more bits representing the at least portion of the physical address in the memory.

18. The method of claim 15, further comprising augmenting the one or more bits of the selected cache line of the page table cache representing the at least portion of the physical address with one or more least significant bits of the intermediate address to produce the translated physical address for the external address.

19. An apparatus, comprising:

at least one processor coupled to a memory; and

an address translation circuit operable to translate a virtual address received from an external device into a physical address of the memory, wherein the address translation circuit includes;

a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate the external address into the physical address; and

a software implemented cache refill function also for managing the at least one address translation table cache,

wherein;

(i) application software, running on the processing system, calls operating system software of the processing system, which controls the hardware implemented cache refill circuit and the software implemented cache refill function, to operate simultaneously in managing the at least one address translation table cache, and to determine which of the hardware implemented cache refill circuit or the software implemented cache refill function is to operate, and which is not to operate, in managing the at least one address translation table cache;

(ii) the hardware implemented cache refill circuit and the software implemented cache refill function are operable to simultaneously refill the at least one address translation table cache; and

(iii) the software implemented cache refill function is operable to pre-load the at least one address translation table cache prior to a cache miss.

20. The apparatus of claim 19, wherein the software implemented cache refill function is operable to reserve one or more cache lines of the at least one address translation table cache and one or more associated physical memory locations, addressed by the physical addresses, in the memory of the processor.

21. The apparatus of claim 20, wherein the software implemented cache refill function is operable to lock one or more of the cache lines of the at least one address translation table cache against a refill by the hardware implemented cache refill circuit.

22. A system, comprising:

an internal memory space;

at least one processor operatively coupled to the memory space;

at least one segment table cache, each cache line of the segment table cache representing a different segment of the memory space;

at least one page table cache, each entry in the page table cache including at least a portion of a physical address in the memory space and belonging to a group of entries representing a page in a given segment of the memory space;

a hardware implemented cache refill circuit for managing the segment and page table caches; and

a software implemented cache refill function also for managing the segment and page table caches,

wherein;

(i) application software, running on the processing system, calls operating system software of the processing system, which controls the hardware implemented cache refill circuit and the software implemented cache refill function, to operate simultaneously in managing the at least one address translation table cache, and to determine which of the hardware implemented cache refill circuit or the software implemented cache refill function is to operate, and which is not to operate, in managing the at least one address translation table cache;

(ii) the hardware implemented cache refill circuit and the software implemented cache refill function are adapted to operate simultaneously; and

(iii) the software implemented cache refill function is operable to pre-load the segment and page table caches prior to a cache miss.