Drive method for MEMS devices

• US 7,889,163 B2
• Filed: 04/29/2005
• Issued: 02/15/2011
• Est. Priority Date: 08/27/2004
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chui, Clarence, Mignard, Marc, Sampsell, Jeffrey B., Kothari, Manish, Mathew, Mithran C.
• Primary Examiner(s): Eisen; Alexander
• Assistant Examiner(s): Mandeville; Jason M
• Application Number:
  US11/118,612
• Publication Number:
  US 20060044928A1
• Time in Patent Office: 2,118 Days
• Field of Search: 359237-275, 345 84-107, 345/204, 345/55
• US Class Current: 345/85
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G09G 2300/0473 Use of light emitting or modulating elements having two or more stable states when no power is applied
• CPC Class Codes: G09G 2300/06 Passive matrix structure, i.e. with direct application of both column and row voltages to the light emitting or modulating elements, other than LCD or OLED
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/3466 based on interferometric effect
• CPC Class Codes: G09G 3/3618 with automatic refresh of the display panel using sense/write circuits

Abstract

Embodiments of exemplary MEMS interferometric modulators are arranged at intersections of rows and columns of electrodes. In certain embodiments, the column electrode has a lower electrical resistance than the row electrode. A driving circuit applies a potential difference of a first polarity across electrodes during a first phase and then quickly transition to applying a bias voltage having a polarity opposite to the first polarity during a second phase. In certain embodiments, an absolute value of the difference between the voltages applied to the row electrode is less than an absolute value of the difference between the voltages applied to the column electrode during the first and second phases.

Claims

1. A display, comprising:

at least one driving circuit;

an array comprising a plurality of interferometric modulators, each of the interferometric modulators being connected to a column electric line and a row electrical line and being configured to be driven by the driving circuit; and

a plurality of circuits connected between the driving circuit and the column electrical lines and the row electrical lines, wherein the circuits are configured to first electrically couple the array to the driving circuit and while the array is electrically coupled to the driving circuit, the driving circuit provides the array with a voltage that is greater than the midpoint of a hysteresis window of the interferometric modulators and that is below an actuation voltage of the interferometric modulators, and after the driving circuit provides the voltage, the circuits are configured to second electrically isolate the array from the driving circuit for an isolation period such that the driving circuit does not provide a voltage to the array during the isolation period, the array maintaining a voltage that is within the hysteresis window during the isolation period, wherein the isolation period is based on a predetermined time constant associated with the array and the plurality of circuits.

2. The display of claim 1, wherein the plurality of circuits each comprise a tri-state circuit.

3. The display of claim 1, wherein the driving circuit includes a row driving element and a column driving element.

4. The display of claim 1, wherein each of the plurality of circuits are connected to a select line from the driving circuit.

5. The display of claim 1, wherein the plurality of circuits electrically isolate the array from the driving circuit for at least 0.001 seconds.

6. The display of claim 1, wherein the plurality of circuits electrically isolate the array from the driving circuit for at least 0.5 seconds.

7. The display of claim 1, wherein the plurality of circuits electrically isolate the array from the driving circuit for at least 2 seconds.

8. The display of claim 1, wherein the driving circuit drives the voltage across each of the interferometric modulators to at least 95% of the actuation voltage of interferometric modulators prior to electrically isolating the array.

9. The display of claim 1, wherein the driving circuit drives the voltage across each of the interferometric modulators to at least 90% of the actuation voltage of interferometric modulators prior to electrically isolating the array.

10. The display of claim 1, wherein the driving circuit drives the voltage across each of the interferometric modulators to at least 75% of the actuation voltage of interferometric modulators prior to electrically isolating the array.

36. The display of claim 1, wherein the plurality of circuits each comprise a tri-state buffer having at least a high impedance state.

37. The display of claim 36, wherein the tri-state buffer has an impedance of about 1 gigaohm in the high impedance state.

38. The display of claim 1, wherein the electrically isolating the array comprises electrically isolating the array from other circuitry.

40. The display of claim 1, wherein the circuits are further configured to electrically isolate the array from the driving circuit based on the time constant associated with the interferometric modulators.

11. A method of controlling a display, the method comprising:

electrically coupling the array of interferometric modulators to at least one driving circuit;

applying a bias voltage to an array of interferometric modulators, wherein the bias voltage is greater than the midpoint of a hysteresis window of the interferometric modulators and the bias voltage is below an actuation voltage of the interferometric modulators, while the array of interferometric modulators is coupled to the at least one driving circuit; and

electrically isolating the array of interferometric modulators from the at least one driving circuit subsequent to applying the bias voltage for an isolation period such that the driving circuit does not provide a voltage to the array during the isolation period, the array maintaining a voltage that is within the hysteresis window during the isolation period, wherein the isolation period is based on a predetermined time constant associated with the array.

12. The method of claim 11, additionally comprising turning-off a charge pump subsequent to electrically isolating the array.

13. The method of claim 11, wherein electrically isolating the array comprises activating a plurality of tri-state circuits.

14. The method of claim 11, wherein electrically isolating the array comprises driving a select line from the driving circuit.

15. The method of claim 11, wherein electrically isolating the array comprises electrically isolating the array from the driving circuit for at least 0.01 seconds.

16. The method of claim 11, wherein electrically isolating the array comprises electrically isolating the array from the driving circuit for at least 0.5 seconds.

17. The method of claim 11, wherein electrically isolating the array comprises electrically isolating the array from the driving circuit for at least 2 seconds.

18. The method of claim 11, wherein applying a bias voltage is performed prior to electrically isolating the interferometric modulators.

19. The method of claim 11, wherein the bias voltage is at least 95% of the actuation voltage of the interferometric modulators.

20. The method of claim 11, wherein the bias voltage is at least 90% of the actuation voltage of the interferometric modulators.

21. The method of claim 11, wherein the bias voltage is at least 75% of the actuation voltage of the interferometric modulators.

39. The method of claim 12, wherein the electrically isolating the array comprises electrically isolating the array from other circuitry.

41. The method of claim 11, wherein electrically isolating the array of interferometric modulators is based on the time constant associated with the interferometric modulators.

22. A system for controlling a display, the system comprising:

means for electrically coupling the array of interferometric modulators to at least one driving circuit;

means for applying a bias voltage to an array of interferometric modulators, wherein the bias voltage is greater than the midpoint of a hysteresis window of the interferometric modulators and the bias voltage is below an actuation voltage of the interferometric modulators, while the array of interferometric modulators is coupled to the at least one driving circuit; and

means for electrically isolating the array of interferometric modulators from the at least one driving circuit subsequent to applying the bias voltage for an isolation period such that the driving circuit does not provide a voltage to the array during the isolation period, the array maintaining a voltage that is within the hysteresis window during the isolation period, wherein the isolation period is based on a predetermined time constant associated with the array and the electrically coupling means.

23. The system of claim 22, wherein the means for electrically isolating the array comprises means for driving a select line from the driving circuit.

24. The system of claim 22, additionally comprising means for applying a bias voltage to each of the interferometric modulators prior to electrically isolating the interferometric modulators.

42. The system of claim 22, wherein the electrically isolating means is configured to isolate the array of interferometric modulators based on the time constant associated with the interferometric modulators.

25. A communications device, comprising:

at least one driving circuit;

an array comprising a plurality of interferometric modulators, each of the interferometric modulators being connected to a column electric line and a row electrical line and being configured to be driven by the driving circuit; and

a plurality of circuits connected between the driving circuit and the column electrical lines and the row electrical lines, wherein the circuits are configured to first electrically couple the array to the driving circuit and while the array is electrically coupled to the driving circuit, the driving circuit provides the array with a voltage that is greater than the midpoint of a hysteresis window of the interferometric modulators and that is below an actuation voltage of the interferometric modulators, and after the driving circuit provides the voltage, the circuits are configured to second electrically isolate the array from the driving circuit for an isolation period such that the driving circuit does not provide a voltage to the array during the isolation period, the array maintaining a voltage that is within the hysteresis window during the isolation period, wherein the isolation period is based on a predetermined time constant associated with the array and the plurality of circuits.

43. The communications device of claim 25, wherein the circuits are further configured to electrically isolate the array from the driving circuit based on the time constant associated with the interferometric modulators.

26. A display, comprising:

at least one driving circuit;

an array comprising a plurality of bi-stable elements, each of the bi-stable elements being connected to a column electric line and a row electrical line and being configured to be driven by the driving circuit; and

a plurality of circuits connected between the driving circuit and each of columns of electrical lines and the row of electrical lines, wherein the circuits are configured to first electrically couple the array to the driving circuit and while the array is electrically coupled to the driving circuit, the driving circuit provides the array with a voltage that is higher than a half of an actuation voltage of the bi-stable elements and that is below the actuation voltage of the bi-stable elements, and after the driving circuit provides the voltage, the circuits are configured to second electrically isolate the array from the driving circuit for an isolation period such that the driving circuit does not provide a voltage to the array during the isolation period, the array maintaining a voltage that is within the hysteresis window during the isolation period, wherein the isolation period is based on a predetermined time constant associated with the array and the plurality of circuits.

27. The display of claim 26, wherein the plurality of circuits each comprise a tri-state circuit.

28. The display of claim 26, wherein the driving circuit includes a row driving element and a column driving element.

29. The display of claim 26, wherein each of the plurality of circuits are connected to a select line from the driving circuit.

30. The display of claim 26, wherein the plurality of circuits electrically isolate the array from the driving circuit for at least 0.01 seconds.

31. The display of claim 26, wherein the plurality of circuits electrically isolate the array from the driving circuit for at least 0.5 seconds.

32. The display of claim 26, wherein the plurality of circuits electrically isolate the array from the driving circuit for at least 2 seconds.

33. The display of claim 26, wherein the driving circuit drives the voltage across each of the bi-stable elements to at least 95% of the actuation voltage of bi-stable elements prior to electrically isolating the array.

34. The display of claim 26, wherein the driving circuit drives the voltage across each of the bi-stable elements to at least 90% of the actuation voltage of the bi-stable elements prior to electrically isolating the array.

35. The display of claim 26, wherein the driving circuit drives the voltage across each of the bi-stable elements to at least 75% of the actuation voltage of bi-stable elements prior to electrically isolating the array.

44. The display of claim 26, wherein the circuits are further configured to electrically isolate the array from the driving circuit based on the time constant associated with the bi-stable elements.