Imaging device and method for high-sensitivity optical scanning and integrated circuit therefor

• US 7,897,902 B2
• Filed: 07/24/2008
• Issued: 03/01/2011
• Est. Priority Date: 06/22/2001
• Status: Expired due to Fees

• Current Assignee: Orbotech Limited (KLA Corporation)
• Original Assignee: Orbotech Limited (KLA Corporation)
• Inventors: Katzir, Yigal, Gur-Arie, Itay, Malinovich, Yacov
• Primary Examiner(s): Epps; Georgia Y
• Assistant Examiner(s): Legasse, Jr.; Francis M
• Application Number:
  US12/179,033
• Publication Number:
  US 20080278775A1
• Time in Patent Office: 950 Days
• Field of Search: 250/214.1, 250/214.R, 250/208.1, 250/214.DC, 348/281, 348/294, 348/282, 348/283, 348/302, 257/431
• US Class Current: 250/208.1
• CPC Class Codes: G01N 21/8851 Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002
• CPC Class Codes: G01N 21/8901 Optical details; Scanning details per se G02B
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/768 for time delay and integration [TDI]
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An inspection system includes a CMOS integrated circuit having integrally formed thereon an at least two dimensional array of photosensors and providing an inspection output representing an object to be inspected. A defect analyzer is operative to receive the inspection output and to provide a defect report.

Claims

1. A single chip integrated circuit suitable for use in an imaging system and comprising:

a CMOS integrated circuit having integrally formed thereon;

an at least two dimensional array of photosensors;

at least one A/D converter receiving outputs from said at least two dimensional array of photosensors;

a plurality of digital registers temporarily storing the outputs of said at least one A/D converter;

a digital memory storing image data provided; and

a plurality of digital adders adding digital values held in said digital registers to corresponding image data stored in said digital memory, such that image data stored in said digital memory is repeatedly summed with the digital values held in said digital registers, and the image data stored in said digital memory comprises a composite sum of the digital values held in said digital registers; and

a row timing block controlling said two dimensional array of photosensors, said digital memory, and said plurality of digital adders, and generating an input pointer and an array clock;

wherein, at each cycle of the array clock, the digital values held in said digital registers are summed by the adders with image data stored in memory cells of said digital memory determined by said input pointer.

2. The single chip integrated circuit recited in claim 1, wherein said two dimensional array of photosensors comprises:

a first group of photosensors, a second group of photosensors, and a third group of photosensors;

first color filters disposed on said first group of photosensors;

second color filters, of a color different from said first color filters, disposed on said second group of photosensors; and

third color filters, of a color different from said first and second color filters, disposed on said third group of photosensors.

3. The single chip integrated circuit recited in claim 1, wherein:

said two dimensional array of photosensors comprises a plurality of columns of photosensors; and

said at least one A/D converter comprises a plurality of A/D converters, each A/D converter receiving outputs from one of said plurality of columns of photosensors.

4. The single chip integrated circuit recited in claim 3, wherein each digital register of said plurality of digital registers temporarily stores the outputs of one of said plurality of A/D converters.

5. The single chip integrated circuit recited in claim 1, wherein said two dimensional array of photosensors comprises a two dimensional array of active pixel sensors.

6. An imaging device, comprising:

an array of sensor elements, arranged in a matrix of sensor rows and sensor columns, each such sensor element being adapted to output a signal responsive to radiation incident thereon;

a memory, comprising memory cells arranged in memory rows and memory columns, each such memory cell being adapted to store a signal value;

one or more adders, adapted to sum the signal output by the sensing elements with the signal value stored in the memory cells; and

timing circuitry, coupled to control the array, memory and adders, and adapted to generate an input pointer and an array clock having clock cycles, such that at each cycle of the array clock, the signal from the sensor elements in each of the sensor rows is summed by the adders with the stored signal value in the cells in a respective one of the memory rows that is determined by the input pointer, thus generating summed signal values that are stored in the memory cells, the timing circuitry further being adapted to advance the input pointer in successive cycles of the array clock so that the summed signal value stored in each of the memory cells comprises a sum of the signals output by a plurality of the sensing elements in a given one of the sensor columns.

7. A method for imaging, using an array of sensor elements, arranged in a matrix of sensor rows and sensor columns, each such sensor element being adapted to output a signal responsive to radiation incident thereon, and a memory, which includes memory cells arranged in memory rows and memory columns, each such memory cell being adapted to store a signal value, the method comprising:

generating an array clock having clock cycles and an input pointer that points to one or more of the memory rows;

at each cycle of the array clock,

summing the signal output by the sensing elements in each of the sensor rows with the signal value stored in the memory cells in a respective one of the memory rows that is determined by the input pointer, thus generating summed signal values that are stored in the memory cells; and

advancing the input pointer in successive cycles of the array clock so that the summed signal value stored in each of the memory cells comprises a sum of the signals output by a plurality of the sensing elements in a given one of the sensor columns.