Known good die using existing process infrastructure

• US 7,898,275 B1
• Filed: 10/01/1998
• Issued: 03/01/2011
• Est. Priority Date: 10/03/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Arnold, Richard W., Riley, Donald E., Wilson, Lester L., Beardain, Weldon, Prevedel, Daniel W.
• Primary Examiner(s): Geyer; Scott B
• Application Number:
  US09/164,580
• Time in Patent Office: 4,534 Days
• Field of Search: 257/48, 324/755, 324/758, 324/528, 324/765, 324/761, 324/158, 324/754, 324/763, 324/500, 324/76.11, 438/11, 438/17, 438/14, 438/15, 438/18
• US Class Current: 324/756.01
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]

Abstract

An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads. The first region is preferably a compliant bump probe tip having a first predetermined height above the layer and includes a standoff on the layer having a second predetermined height above the layer less than the first height.

Claims

1. An apparatus for testing a semiconductor die which comprises:

(a) a package having a cavity therein;

(b) a plurality of terminals in said package disposed at the periphery of said cavity;

(c) a semiconductor die to be tested having a plurality of bond pads thereon, said die disposed in said cavity;

(d) an interconnecting layer having electrically conductive paths thereon disposed in said cavity, each of said paths having first and second spaced apart regions thereon, said first region of each path being aligned with and contacting a said bond pad, said first region including a compliant bump probe tip having a first predetermined height above said layer and further including a standoff on said layer having a second predetermined height above said layer less than said first height; and

(e) an interconnection between said second spaced apart region of each of said paths and one of said plurality of terminals.

2. The apparatus of claim 1 wherein said second spaced apart region of each of said paths is a bump aligned with and contacting one of said plurality of terminals.

3. The apparatus of claim 1 further including a compliant layer disposed over said interconnecting layer and providing a force causing engagement of at least said first spaced apart regions and said bond pads.

4. The apparatus of claim 2 further including a compliant layer disposed over said interconnecting layer and providing a force causing engagement of at least said first spaced apart regions and said bond pads.

5. An interconnecting layer for use in a semiconductor package which comprises;

(a) an electrically insulating layer;

(b) electrically conductive paths on said layer, each of said paths having first and second spaced apart regions thereon, said second spaced apart region of each of said paths having a compliant bump having a height greater than all other structures on said layer; and

(c) a standoff disposed on said layer and having a height above said layer and less than said bump.

6. The layer of claim 5 wherein said second region is a bump extending above the level of said electrically conductive path.

7. The layer of claim 6 wherein said layer is flexible.

8. The layer of claim 5 wherein said layer is flexible.

9. An apparatus adaptable for the testing of semiconductor devices comprising:

a package; and

an interconnecting medium contained within said package having electrical paths adaptable for coupling to test circuitry, wherein said interconnecting medium includes a medium surface, a plurality of standoffs affixed to said medium surface, and a plurality of probe tips affixed to said medium surface, said probe tips adaptable for making electrical contact with pads on said semiconductor device, wherein said probe tips are compliant bump probe tips.

10. The apparatus of claim 9, said package further comprising:

a package base having an upper surface adapted to receive said interconnecting medium, said medium having a medium lower surface;

a bonding layer interposed between said medium lower surface and said package base upper surface; and

a package lid having a lower surface adapted to receive said semiconductor device, wherein said package lid is positioned above said package base.

11. The apparatus of claim 10, wherein said bonding layer is comprised of an elastomeric material.

12. The apparatus of claim 10, wherein said semiconductor device is a die having an upper surface, said upper surface fixed to said package lid lower surface by a bonding layer interposed therebetween.

13. The apparatus of claim 10, wherein said semiconductor device is a wafer having an upper surface, said upper surface fixed to said package lid lower surface by a bonding layer interposed therebetween.

14. The apparatus of claim 13, wherein said bonding layer interposed between said die and said package lid lower surface is comprised of an elastomeric material.

15. The apparatus of claim 9, wherein the compliant bump probe tips are comprised of a solid material.

16. An apparatus adaptable for the testing of semiconductor devices comprising:

a package, wherein said package has a package lid having a lower surface adapted for receiving said semiconductor device, said semiconductor device having an upper surface, and a package base having an upper surface;

an interconnecting medium contained within said package, wherein said interconnecting medium has electrical paths adaptable for coupling to test circuitry, said medium including a medium surface, said medium surface having a plurality of probe tips affixed thereto, a plurality of standoffs affixed thereto, and a lower surface, wherein said probe tips are adaptable for making electrical contact with pads on said semiconductor device and are compliant bump probe tips;

a bonding layer comprising an elastomeric material interposed between said package lid lower surface and said semiconductor device upper surface; and

a bond layer comprising an elastomeric material interposed between said interconnecting medium lower surface and said package base upper surface, said package base being adapted for receiving said interconnecting medium.

17. The apparatus of claim 16, wherein the compliant bump probe tips are comprised of a solid material.