Compensation capacitor network for divided diffused resistors for a voltage divider

• US 7,902,907 B2
• Filed: 12/12/2007
• Issued: 03/08/2011
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Hiltunen; Thomas J
• Application Number:
  US11/954,763
• Publication Number:
  US 20090153237A1
• Time in Patent Office: 1,182 Days
• Field of Search: None
• US Class Current: 327/536
• CPC Class Codes: H01L 27/0802 Resistors only

Abstract

A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is connected across the resistors and the voltage divider output. The feed-forward capacitor network allows the output to rise and fall quickly with a change in the voltage divider input. Accordingly, an improved frequency response should be obtained utilizing divided diffused resistors.

Claims

1. An integrated circuit comprising:

a first plurality of diffused resistors arranged in series for a voltage divider, the voltage divider comprising;

an output node;

an input node coupled to an input voltage; and

a reference node coupled to a voltage reference;

a first diffused resistor having a first terminal and a second terminal, wherein the first diffused resistor is of a first semiconductor type and is disposed in a first well of a second semiconductor type, wherein the first terminal is coupled to the output node and wherein the second terminal of the first diffused resistor is coupled to the reference node;

a second plurality of diffused resistors arranged in series between the input node and the output node, wherein each of the second plurality of diffused resistors is of the first semiconductor type and is disposed in its own well of the second semiconductor type, wherein the second plurality of diffused resistors consists of each resistor arranged in series between the input node and the output node; and

a plurality of explicit capacitors arranged in series, wherein each of the plurality of explicit capacitors is coupled directly in parallel with a respective one of each diffused resistor of the second plurality of diffused resistors;

wherein there is not an explicit capacitor in parallel with the first diffused resistor.

2. The integrated circuit of claim 1, wherein the first well for the first diffused resistor is coupled to the first terminal and to the output node.

3. The integrated circuit of claim 1, wherein the second plurality of diffused resistors comprises at least a second diffused resistor and a third diffused resistor, further comprising a fourth diffused resistor disposed in the first well, the fourth diffused resistor having a first terminal and a second terminal, wherein the first terminal is coupled to the first well and directly or indirectly to the second node of the second diffused resistor, and wherein the second terminal of the fourth diffused resistor is coupled to the output node and to the first terminal of the first diffused resistor.

4. The integrated circuit of claim 1, wherein the voltage reference coupled to the reference node is ground.

5. The integrated circuit of claim 1, wherein the resistors of the voltage divider have a total electrical resistance of between about 1 kΩ

and 10 MΩ

.

6. The integrated circuit of claim 1, wherein the resistors of the voltage divider have a total electrical resistance of between about 100 kΩ

and 1 MΩ

.

7. The integrated circuit of claim 1, wherein each of the plurality of capacitors has a capacitance of between about 0.1 picofarad (pF) and 1.0 microfarad (μ

F).

8. The integrated circuit of claim 1, wherein each of the plurality of capacitors has a capacitance of between about 1.0 pF and 10 μ

F.

9. The integrated circuit of claim 1, wherein the first type semiconductor comprises a p-type semiconductor, and the second type semiconductor comprises an n-type semiconductor.

10. The integrated circuit of claim 1, wherein the first type semiconductor comprises an n-type semiconductor, and the second type semiconductor comprises a p-type semiconductor.

11. An integrated circuit comprising:

a charge pump circuit;

a first plurality of diffused resistors arranged in series for a voltage divider, the voltage divider comprising;

an output node;

an input node coupled to an input voltage; and

a reference node coupled to a voltage reference;

a first diffused resistor having a first terminal and a second terminal, wherein the first diffused resistor is of a first semiconductor type and is disposed in a first well of a second semiconductor type, wherein the first terminal is coupled to the output node and wherein the second terminal of the first diffused resistor is coupled to the reference node;

a second plurality of diffused resistors arranged in series between the input node and the output node, wherein each of the second plurality of diffused resistors is of the first semiconductor type and is disposed in its own well of the second semiconductor type; and

a plurality of explicit capacitors arranged in series, wherein each of the plurality of explicit capacitors is coupled directly in parallel with a respective diffused resistor of at least a shunted portion of the second plurality of diffused resistors in series between the input node and the output node;

wherein there is not an explicit capacitor in parallel with the first diffused resistor;

wherein an output voltage of the charge pump circuit is coupled to the input node of the voltage divider as the input voltage, and wherein the output node of the voltage divider is coupled to a feedback control input of the charge pump circuit.

12. The integrated circuit of claim 11, wherein the second plurality of diffused resistors consists of each resistor arranged in series between the input node and the output node, wherein the shunted portion of the second plurality of diffused resistors comprises the entire second plurality of diffused resistors such that each capacitor of the plurality is coupled directly in parallel with a respective diffused resistor of the second plurality of diffused resistors.

13. The integrated circuit of claim 11, wherein the output voltage of the charge pump circuit is supplied to a memory.

14. The integrated circuit of claim 11, wherein the integrated circuit comprises a flash memory device.

15. A method of fabricating an integrated circuit, the method comprising:

forming a first plurality of diffused resistors arranged in series for a voltage divider, wherein forming the first plurality further comprises;

forming a first diffused resistor having a first terminal and a second terminal, wherein the first diffused resistor is of a first semiconductor type and is disposed in a first well of a second semiconductor type, wherein the first terminal is coupled to an output node and wherein the second terminal of the first diffused resistor is coupled to a reference node, wherein the reference node is coupled to a voltage reference;

forming a second plurality of diffused resistors arranged in series between an input node and the output node, wherein the input node is coupled to an input voltage, wherein each of the second plurality of diffused resistors is of the first semiconductor type and is disposed in its own well of the second semiconductor type, wherein the second plurality of diffused resistors consists of each resistor arranged in series between the input node and the output node;

forming a plurality of explicit capacitors arranged in series, wherein each of the plurality of explicit capacitors is coupled directly in parallel with a respective one of each diffused resistor of at least a shunted portion of the second plurality of diffused resistors between the input node and the output node; and

not forming an explicit capacitor in parallel with the first diffused resistor.

16. The method of claim 15, wherein the first type semiconductor comprises a p-type semiconductor, and the second type semiconductor comprises an n-type semiconductor.

17. The method of claim 15, wherein the first type semiconductor comprises an n-type semiconductor, and the second type semiconductor comprises a p-type semiconductor.

18. The method of claim 15, wherein the act of forming a well is performed at the same time that a bulk of one or more MOSFETs is formed.

19. The method of claim 15, wherein the act of forming the diffused resistors is performed at the same time that source and drain regions of one or more MOSFETs are formed.