Mode indicator for interferometric modulator displays

• US 7,903,047 B2
• Filed: 04/17/2006
• Issued: 03/08/2011
• Est. Priority Date: 04/17/2006
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Cummings, William
• Primary Examiner(s): Nguyen; Kevin M
• Application Number:
  US11/405,116
• Publication Number:
  US 20070242008A1
• Time in Patent Office: 1,786 Days
• Field of Search: 345/204, 345/3.1, 345/1.1
• US Class Current: 345/3.1
• CPC Class Codes: G09G 2300/0473 Use of light emitting or modulating elements having two or more stable states when no power is applied
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

A method and apparatus for displaying data on bi-stable and non-bi-stable displays is provided. The apparatus includes a controller chip capable of being connected to a non-bi-stable display through a first interface channel and also capable of being connected to a bi-stable display via the first interface channel and an additional second interface channel. When connected the non-bi-stable display, the second interface channel is not connected. The second interface channel may carry mode information bits to the bi-stable display module to allow the bi-stable display to utilize power-saving features.

Claims

1. A display device comprising:

a single controller adaptable to output image data via a first set of interface wires to any of a first display module that is a non-bi-stable display module and a second display module that is a bi-stable display module for displaying the image data, the first display module including a first array driver and a first display array, the second display module including a second array driver and a second display array, the second display array being distinct and separate from the first display array, the controller further configured to output control data via a second set of interface wires to only the second display module for controlling an additional feature of the second display module wherein the additional feature of the second display module is unavailable to the first display module.

2. The display device of claim 1, wherein the control data is used by the second display module to determine what portion of the image data will be displayed.

3. The display device of claim 2, wherein the portion of the image data to be displayed is all the image data.

4. The display device of claim 2, wherein the portion of the image data to be displayed is none of the image data.

5. The display device of claim 2, wherein the portion of the image data to be displayed is only part of the image data.

6. The display device of claim 1, wherein the control data comprises mode data.

7. The display device of claim 1, wherein the bi-stable display module includes an electromechanical system display.

8. A single video controller chip comprising:

a processor configured to analyze received image data and determine a display mode for the image data;

a first output circuit being adaptable to communicate with any of a non-bi-stable display and a bi-stable display array via a first set of interface wires, wherein the non-bi-stable display is distinct and separate from the bi-stable display array; and

a second output circuit being adaptable to carry the display mode to only the bi-stable display array via a second set of interface wires when the bi-stable display array is coupled to both the first set of interface wires and the second set of interface wires.

9. The video controller chip of claim 8, wherein the processor determines the display mode based on an attribute of the received image data.

10. The video controller chip of claim 8, wherein the processor determines the display mode by predicting the content of the received image data based on a system event.

11. The apparatus of claim 8, further comprising:

a display;

another processor that is configured to communicate with said display, said another processor being configured to process the image data; and

a memory device that is configured to communicate with the another processor.

12. The apparatus as recited in claim 11, further comprising a driver circuit configured to send at least one signal to said display.

13. The apparatus as recited in claim 12, further comprising a controller configured to send at least a portion of said image data to said driver circuit.

14. The apparatus as recited in claim 8, further comprising an image source module configured to send said image data to said processor.

15. The apparatus as recited in claim 14, wherein said image source module comprises at least one of a receiver, transceiver, and transmitter.

16. The apparatus as recited in claim 8, further comprising an input device configured to receive input data and to communicate said input data to said processor.

17. A single video controller chip comprising:

means for adaptably outputting first data, via a first set of interface wires, to any one of a first means for displaying data comprising a plurality of non-bi-stable display elements and a second means for displaying data comprising a plurality of bi-stable display elements, wherein the first means for display data is distinct and separate from the second means for displaying data; and

means for adaptably outputting second data, via a second set of interface wires, to only the second means for display data,

wherein the second data is configured to control a temporal dithering means of the second means for displaying data.

18. The single video controller chip of claim 17, wherein the temporal dithering means of the second means for displaying data is unavailable to the first means for displaying data.

19. The single video controller chip of claim 17, wherein the data outputted to the second means for displaying data comprises mode indictor data comprising instructions to activate the temporal dithering means.

20. The single video controller chip of claim 17, wherein the second data comprises mode data.

21. The single video controller chip of claim 17, wherein the first data comprises image data.

22. The single video controller chip of claim 21, wherein the temporal dithering means causes a high bit-depth effect.

23. The single video controller chip of claim 21, wherein the temporal dithering means causes a gray-scale effect.

24. The single video controller chip of claim 19, wherein the temporal dithering means is activated in response to receiving video data.

25. The single video controller chip of claim 17, wherein the second data is used by the second means for displaying data to determine at least some of the plurality of display elements to be dithered.

26. The single video controller chip of claim 17, wherein the plurality of bi-stable display elements comprise interferometric display elements.

27. The single video controller chip of claim 17, wherein the second means for displaying data includes an electromechanical system display.