Semiconductor device having an elevated source/drain structure of varying cross-section

• US 7,906,809 B2
• Filed: 11/17/2008
• Issued: 03/15/2011
• Est. Priority Date: 04/25/2005
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Aiso, Fumiki
• Primary Examiner(s): Such; Matthew W
• Application Number:
  US12/272,036
• Publication Number:
  US 20090072324A1
• Time in Patent Office: 848 Days
• Field of Search: 438/300, 257/288, 257330-332, 257/E21.43, 257/E29.267
• US Class Current: 257/330
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.

Claims

1. A semiconductor device comprising:

an isolation region selectively formed in a semiconductor substrate,

a gate wiring structure selectively formed on the semiconductor substrate, the semiconductor substrate thereby having first and second surface portions defined by the isolation region and the gate wiring structure, each of the first and second surface portions including a plurality of side edges, at least one of the side edges being defined by the gate wiring structure and the remaining ones of the side edges being defined by the isolation region; and

elevated source and drain regions formed respectively on the first and second surface portions, each of the elevated source and drain regions including a lower surface which is in contact with an associated one of the first and second surface portions with the same shape as the associated one of the first and second surface portions and an upper surface which is substantially the same as the lower surface and aligned with the lower surface, each of the elevated source and drain regions further including a side surface which protrudes from an associated one of the remaining ones of the side edges of a corresponding one of the first and second surface portions on a slant in a direction of the isolation region without substantially contacting with the isolation region, followed by slanting in an opposite direction to the isolation region to terminate the upper surface, wherein a cross-sectional area of each elevated source and drain region in any plane parallel to the substrate is greater than the area of the upper or lower surfaces thereof.

2. The semiconductor device according to claim 1, wherein the isolation region comprises an STI structure.

3. The semiconductor device according to claim 1, wherein the gate wiring structure comprises a gate insulating film formed on the semiconductor substrate between the first and second portions, a gate electrode formed on the gate insulating film and side walls formed on side surfaces of the gate insulating film and the gate electrode.