Method for improving power-supply rejection

• US 7,907,003 B2
• Filed: 01/14/2009
• Issued: 03/15/2011
• Est. Priority Date: 01/14/2009
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Illegems, Paul F., Pulijala, Srinivas K.
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Cole; Brandon S
• Application Number:
  US12/353,843
• Publication Number:
  US 20100176875A1
• Time in Patent Office: 790 Days
• Field of Search: 327/530, 327538-543, 327/546, 323312-317
• US Class Current: 327/541
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

An electronic circuit may comprise an input stage powered by a supply voltage and configured to receive a reference signal. The circuit may further comprise an output stage powered by the supply voltage and coupled to the input stage, and configured to generate an error signal based on: the reference signal, and a feedback signal based on an output signal. The circuit may also include a pass transistor powered by the supply voltage and configured to generate the output signal based on the error signal. A capacitor coupled between the supply voltage and the output stage may increase the current flowing in the output stage, resulting in the output stage conducting current even during a rising edge of the supply voltage, preventing the output signal from reaching the level of the supply voltage during the rising edge of the supply voltage.

Claims

1. An electronic circuit comprising:

an output node;

a first input transistor having;

a first channel terminal configured to draw a first portion of a first current generated from a supply voltage; and

a control terminal configured to receive a reference input;

a second input transistor having;

a first channel terminal configured to draw a second portion of the first current; and

a control terminal configured in a feedback loop with the output node;

a first output transistor having;

a first channel terminal coupled to the output node and configured to draw a second current generated from the supply voltage;

a second channel terminal coupled to a second channel terminal of the first input transistor; and

a control terminal configured to receive a biasing signal;

a second output transistor having;

a first channel terminal configured to draw a third current generated from the supply voltage;

a second channel terminal coupled to a second channel terminal of the second input transistor; and

a control terminal configured to receive the biasing signal;

a third output transistor having;

a first channel terminal coupled to the second channel terminal of the first output transistor;

a second channel terminal coupled to a reference voltage; and

a control terminal coupled to a control node;

a fourth output transistor having;

a first channel terminal coupled to the second channel terminal of the second output transistor;

a second channel terminal coupled to the reference voltage; and

a control terminal coupled to the control node; and

a capacitor coupled between the supply voltage and the control node to prevent the first and second transistors from turning off during a rising edge of the supply voltage, to prevent an output voltage generated at the output node from rising during the rising edge of the supply voltage.

2. The electronic circuit of claim 1, further comprising a pass transistor having a control terminal coupled to the first channel terminal of the first output transistor;

and a channel coupled between the supply voltage and the output node.

3. The electronic circuit of claim 2, wherein the pass transistor is a PMOS device.

4. The electronic circuit of claim 1, further comprising a voltage divider circuit, the voltage divider circuit comprising:

a first resistor coupled between the output node and the control terminal of the first input transistor; and

a second resistor coupled between the control terminal of the first input transistor and the reference voltage.

5. The electronic circuit of claim 1, wherein the first and second input transistors are PMOS devices, and wherein the first, second, third, and fourth output transistors are NMOS devices.

6. The electronic circuit of claim 1, wherein the reference voltage is signal ground.

7. The electronic circuit of claim 1, further comprising a second capacitor coupled between the control node and the output node to achieve frequency compensation.

8. The electronic circuit of claim 1, further comprising:

a first current mirror circuit coupled to the supply voltage and configured to generate a bias current, wherein the first current is a mirrored current of the bias current; and

a second current mirror circuit coupled to the supply voltage and configured to generate the second current, wherein the second current is a mirrored current of the third current.

9. A voltage regulator comprising:

a regulator output configured to provide a regulated voltage;

an error amplifier powered by a supply voltage, and having a first input configured to receive a reference signal;

a pass transistor having a control terminal coupled to an output of the error amplifier;

wherein the channel of the pass transistor is coupled between the supply voltage and the regulator output;

wherein the regulator output is coupled to a second input of the error amplifier to form a feedback control loop;

wherein the error amplifier comprises an output stage configured to provide an output signal at the output of the error amplifier; and

wherein the error amplifier is configured to control the output stage of the error amplifier to conduct current during a rising edge of the supply voltage to prevent the regulated output voltage from rising during the rising edge of the supply voltage.

10. The voltage regulator of claim 9, further comprising:

a first resistor coupled between the second input of the error amplifier and the regulator output; and

a second resistor coupled between the regulator output and a voltage reference.

11. The voltage regulator of claim 9, wherein the error amplifier comprises:

a first input transistor having;

a first channel terminal configured to draw a first portion of a first current generated from the supply voltage; and

a control terminal configured as the first input of the error amplifier; and

a second input transistor having;

a first channel terminal configured to draw a second portion of the first current; and

a control terminal configured as the second input of the error amplifier.

12. The voltage regulator of claim 11, wherein the output stage of the error amplifier comprises:

a first output transistor having;

a first channel terminal coupled to the regulator output and configured to draw a second current generated from the supply voltage;

a second channel terminal coupled to a second channel terminal of the first input transistor; and

a control terminal configured to receive a biasing signal;

a second output transistor having;

a first channel terminal configured to draw a third current generated from the supply voltage;

a second channel terminal coupled to a second channel terminal of the second input transistor; and

a control terminal configured to receive the biasing signal;

a third output transistor having;

a first channel terminal coupled to the second channel terminal of the first output transistor;

a second channel terminal coupled to a voltage reference; and

a control terminal coupled to a control node; and

a fourth output transistor having;

a first channel terminal coupled to the second channel terminal of the second output transistor;

a second channel terminal coupled to the voltage reference; and

a control terminal coupled to the control node.

13. The voltage regulator of claim 12, further comprising a capacitor coupled between the control node and the regulator output achieve frequency compensation.

14. The voltage regulator of claim 12, further comprising a capacitor configured to effect additional current to flow through respective channels of the third and fourth output transistors, to prevent the first and second output transistors from turning off during a rising edge of the supply voltage.

15. A method for operating an electronic circuit, the method comprising:

providing a supply voltage to the electronic circuit;

providing a reference signal to the electronic circuit;

generating an output signal based on the supply voltage, the reference signal, and an error signal;

generating a feedback signal based on the output signal;

an output stage of the electronic circuit generating the error signal based on the supply voltage, the reference signal, and the feedback signal; and

controlling the output stage from within the electronic circuit to have the output stage continue to conduct current during a rising edge of the supply voltage to prevent the output signal from rising to the level of the supply voltage during the rising edge of the supply voltage.

16. The method of claim 15, wherein said controlling comprises preventing a pair of cascode transistors configured in the output stage of the electronic circuit from turning off during the rising edge of the supply voltage.

17. The method of claim 16, wherein said preventing comprises causing an additional current to flow through a pair of output transistors having their respective channels coupled between respective channel terminals of the pair of cascode transistors and a voltage reference.

18. An electronic circuit comprising:

an input stage powered by a supply voltage and configured to receive a reference signal;

an output stage powered by the supply voltage and coupled to the input stage, and configured to generate an error signal based on;

the reference signal, and a feedback signal based on an output signal;

a pass transistor powered by the supply voltage and configured to generate the output signal based on the error signal; and

a capacitor coupled between the supply voltage and the output stage to increase current flowing in the output stage to have the output stage conduct current even during a rising edge of the supply voltage to prevent the output signal from reaching the level of the supply voltage during the rising edge of the supply voltage.

19. The electronic circuit of claim 18, wherein the input stage is a differential input stage comprising PMOS devices, and wherein the output stage is a cascode output stage comprising NMOS devices.

20. The electronic circuit of claim 18, wherein the pass transistor is a PMOS device.