System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter

• US 7,910,447 B1
• Filed: 05/15/2007
• Issued: 03/22/2011
• Est. Priority Date: 05/15/2007
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Adler, Steven J., Xu, Mingwei
• Primary Examiner(s): Such; Matthew W
• Assistant Examiner(s): Naraghi; Ali
• Application Number:
  US11/803,539
• Time in Patent Office: 1,407 Days
• Field of Search: 438309-378, 257/E21.372, 257/E21.38
• US Class Current: 438/309
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/66287 with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation H01L29/6628 takes precedence
• CPC Class Codes: H01L 29/7322 having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

Abstract

A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

Claims

1. A method of manufacturing a self aligned bipolar transistor comprising the steps of:

forming an active region of the transistor;

forming a silicon nitride sacrificial emitter above the active region of the transistor;

depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter using a physical vapor deposition process;

exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process;

performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window;

depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window;

forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and

performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose an underlying base portion of the transistor.

2. The method as claimed in claim 1 wherein a thickness of the physical vapor deposition oxide layer over side walls of the silicon nitride sacrificial emitter is at most fifteen nanometers.

3. The method as claimed in claim 1 wherein the physical vapor deposition process deposits the physical vapor deposition oxide layer anisotropically.

4. The method as claimed in claim 1 further comprising the step of:

performing a third etch process to remove portions of the physical vapor deposition oxide layer from side walls of the silicon nitride sacrificial emitter.

5. The method as claimed in claim 4 wherein the third etch process comprises an isotropic wet etch process.

6. The method as claimed in claim 4 further comprising the steps of:

performing a diluted hydrofluoric acid etch process to open the emitter window to the active region of the transistor; and

forming an emitter structure in the emitter window.

7. A method of manufacturing a self aligned bipolar transistor comprising the steps of:

forming an active region of the transistor that comprises a collector portion covered by a base portion covered by a silicon oxide material;

forming a silicon nitride sacrificial emitter on the silicon oxide material above the active region of the transistor;

removing portions of the silicon oxide material that are not under the silicon nitride sacrificial emitter;

growing an in-situ layer of silicon/polysilicon on an external base region of the base portion of the transistor;

depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter and over the layer of silicon/polysilicon using a physical vapor deposition process;

exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process;

performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window;

depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window;

forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and

performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose the underlying base portion of the transistor.

8. The method as claimed in claim 7 wherein a thickness of the physical vapor deposition oxide layer over side walls of the silicon nitride sacrificial emitter is at most fifteen nanometers.

9. The method as claimed in claim 7 further comprising the steps of:

performing a third etch process to remove portions of the physical vapor deposition oxide layer from side walls of the silicon nitride sacrificial emitter.

10. The method as claimed in claim 9 further comprising the steps of:

performing a diluted hydrofluoric acid etch process to remove portions of the silicon oxide material to open the emitter window to the base region of the transistor; and

forming an emitter structure in the emitter window.

11. The method as claimed in claim 7 wherein the oxide spacer layer comprises a tetraethyloxysilane layer having a thickness of approximately twenty nanometers.

12. The method as claimed in claim 10 wherein the step of forming the emitter structure in the emitter window comprises the steps of:

depositing a polysilicon layer to form a polysilicon emitter in the emitter window;

masking a central portion on the polysilicon layer; and

performing a fifth etch process to remove portions of the polysilicon layer and portions of the physical vapor deposition oxide layer that are not located under the mask.

13. The method as claimed in claim 12 wherein the step of forming the emitter structure in the emitter window further comprises the steps of:

masking with a polybase mask the central portion of the polysilicon layer and portions of the silicon/polysilicon layer that are adjacent to the emitter window; and

performing a sixth etch process to remove portions of the silicon/polysilicon layer and portions of the base portion of the transistor that are not under the polybase mask.

14. A method of manufacturing a self aligned bipolar transistor comprising the steps of:

forming an active region of the transistor that comprises a collector portion covered by a base portion covered by a silicon oxide material;

forming a silicon nitride sacrificial emitter on the silicon oxide material above the active region of the transistor;

removing portions of the silicon oxide material that are not under the silicon nitride sacrificial emitter;

performing a self aligned base implantation process on an external base region of the base portion of the transistor;

depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter using a physical vapor deposition process;

exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process;

performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window;

depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window;

forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and

performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose the underlying base portion of the transistor.

15. The method as claimed in claim 14 wherein a thickness of the physical vapor deposition oxide layer over side walls of the silicon nitride sacrificial emitter is at most fifteen nanometers.

16. The method as claimed in claim 14 further comprising the steps of:

performing a third etch process to remove portions of the physical vapor deposition oxide layer from side walls of the silicon nitride sacrificial emitter.

17. The method as claimed in claim 16 further comprising the steps of:

performing a diluted hydrofluoric acid etch process to remove portions of the silicon oxide material to open the emitter window to the base region of the transistor; and

forming an emitter structure in the emitter window.

18. The method as claimed in claim 14 wherein the oxide spacer layer comprises a tetraethyloxysilane layer having a thickness of approximately twenty nanometers.

19. The method as claimed in claim 17 wherein the step of forming the emitter structure in the emitter window comprises the steps of:

depositing a polysilicon layer to form a polysilicon emitter in the emitter window;

masking a central portion on the polysilicon layer; and

performing a fifth etch process to remove portions of the polysilicon layer and portions of the physical vapor deposition oxide layer that are not located under the mask.

20. The method as claimed in claim 19 wherein the step of forming the emitter structure in the emitter window further comprises the steps of:

masking with a polybase mask the central portion of the polysilicon layer and portions of the base portion of the transistor that are adjacent to the emitter window; and

performing a sixth etch process to remove portions of the base portion of the transistor that are not under the polybase mask.