Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink

• US 7,910,993 B2
• Filed: 07/10/2006
• Issued: 03/22/2011
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Imthurn, George P., Kelly, Dylan J., Welstand, Robert B., Burgener, Mark L., Kemerling, Clint L., Stuber, Michael A., Brindle, Christopher N.
• Primary Examiner(s): NGUYEN, NIKI HOANG
• Assistant Examiner(s): Nguyen; Tram H
• Application Number:
  US11/484,370
• Publication Number:
  US 20070018247A1
• Time in Patent Office: 1,716 Days
• Field of Search: 257/347, 257/59, 257/61, 257/333, 257/346, 257/327, 257/40, 257/402, 257/403, 257314-326, 257/105, 257/288, 257/401, 257/901
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. An accumulated charge control (ACC) floating body MOSFET (ACC MOSFET), adapted to control nonlinear response of the MOSFET when the MOSFET is operated in an accumulated charge regime, comprising:

a) a MOSFET having a floating body, wherein the MOSFET is biased to selectively operate in the accumulated charge regime, and wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in the accumulated charge regime; and

b) an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET, wherein, when the MOSFET is operated in the accumulated charge regime, an ACS bias voltage (V_ACS) is applied to the ACS to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the ACS;

wherein the MOSFET includes a gate, drain, source, and a gate oxide layer positioned between the gate and the body, and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in an off-state (non-conducting state), and wherein charge accumulates within the body in a region proximate the gate oxide;

wherein the MOSFET body includes a channel region including a gate modulated conductive channel between the source and the drain, and wherein the source, drain and channel have carriers of identical polarity when the MOSFET is biased to operate in an on-state (conducting state), and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in the off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain and channel carriers.

2. The ACC MOSFET of claim 1, wherein the MOSFET comprises an NMOSFET device, and wherein the accumulated charge comprises holes having “

P”

polarity.

3. The ACC MOSFET of claim 2, wherein the MOSFET comprises an enhancement mode NMOSFET device.

4. The ACC MOSFET of claim 2, wherein the MOSFET comprises a depletion mode NMOSFET device.

5. The ACC MOSFET of claim 1, wherein the MOSFET has an inherent linearity characteristic, and wherein the linearity of the ACC MOSFET is improved by removing or otherwise reducing the accumulated charge from the MOSFET body.

6. The ACC MOSFET of claim 1, wherein the MOSFET has an inherent drain-to-source breakdown voltage (BVDSS) characteristic, and wherein the BVDSS characteristic of the ACC MOSFET is improved by removing or otherwise reducing the accumulated charge from the MOSFET body.

7. The ACC MOSFET of claim 1, wherein the MOSFET has a drain-to-source off-state capacitance (C_off) when operated in the off-state (non-conducting state), and wherein the off-state capacitance (C_off) exhibits improved linearity characteristics by removing or otherwise reducing the accumulated charge from the MOSFET body.

8. The ACC MOSFET of claim 7, wherein the off-state capacitance (C_off) has an inherent magnitude, and wherein the magnitude of the off-state capacitance (C_off) is decreased by removing or otherwise reducing the accumulated charge from the MOSFET body.

9. The ACC MOSFET of claim 7, wherein the off-state capacitance (C_off) varies over time in a presence of a time varying drain-to-source bias voltage (Vds), and wherein the variations of C_off over time are reduced by removing or otherwise reducing the accumulated charge from the MOSFET body.

10. The ACC MOSFET of claim 7, wherein the off-state capacitance (C_off) varies over time as the accumulated charge accumulates in the MOSFET body, and wherein the variations of C_off over time are reduced by removing or otherwise reducing the accumulated charge from the MOSFET body.

11. The ACC MOSFET of claim 1, wherein the ACS has an impedance greater than approximately 10⁶ ohms.

12. The ACC MOSFET of claim 1, wherein the ACS has an impedance less than approximately 10⁶ ohms.

13. The ACC MOSFET of claim 1, wherein the ACC MOSFET has an inherent power handling capability, and wherein the ACC MOSFET is capable of processing input signals having increased power levels by removing or otherwise reducing the accumulated charge from the MOSFET body.

37. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a silicon-on-insulator technology.

14. An accumulated charge control floating body MOSFET (ACC MOSFET) adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising:

a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is operated in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer; and

b) a first accumulated charge sink (ACS) positioned proximate a first distal end of the floating body, wherein the first ACS is in electrical communication with the floating body, and wherein, when the MOSFET is operated in the accumulated charge regime, an ACS bias voltage (V_ACS) is applied to the ACS to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the ACS; and

an electrical contact region positioned proximate to and in electrical communication with the first ACS, wherein the electrical contact region facilitates electrical coupling to the first ACS.

15. The ACC MOSFET of claim 14, wherein the ACC MOSFET comprises an ACC NMOSFET, and wherein the source and drain both comprise N+ doped regions, the floating body and the first ACS both comprise P−

doped regions, and the electrical contact region comprises a P+ doped region.

16. The ACC MOSFET of claim 14, wherein the electrical contact region and the ACS are coextensive.

17. The ACC MOSFET of claim 15, wherein the floating body and the ACS comprise a combined P−

doped region that may be fabricated in a single ion-implementation manufacturing step.

18. The ACC MOSFET of claim 14, wherein the MOSFET body includes a channel region including a gate modulated conductive channel between the source and the drain, and wherein the source, drain and channel have carriers of identical polarity when the ACC MOSFET is operated in an on-state (conducting state), and wherein the ACC MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in the off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain and channel carriers.

19. The ACC MOSFET of claim 18, wherein the ACC MOSFET comprises an NMOSFET device, and wherein the accumulated charge comprises holes having “

P”

polarity.

20. The ACC MOSFET of claim 18, wherein the ACC MOSFET has a depleted or partially depleted channel region.

21. The ACC MOSFET of claim 14, wherein the ACS has an impedance greater than approximately 10⁶ ohms.

22. The ACC MOSFET of claim 14, wherein the ACS is positioned a selected distance away from the source and drain thereby reducing parasitic capacitance effects associated with the ACS.

23. The ACC MOSFET of claim 14, wherein the ACS is coupled to the body at the first distal end of the floating body thereby reducing parasitic capacitance effects associated with the coupling of the ACS to the floating body.

24. The ACC MOSFET of claim 14, wherein the floating body has a width exceeding approximately 10 μ

m.

25. The ACC MOSFET of claim 14, wherein the ACC MOSFET includes a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS.

26. The ACC MOSFET of claim 25, wherein the gate, drain, source and ACS terminals are coupled to their respective regions via low resistance contact regions.

27. The ACC MOSFET of claim 25, wherein the ACC MOSFET is biased to operate in the accumulated charge regime by applying selected bias voltages to the source, drain and gate terminals, and wherein accumulated charge is removed or otherwise controlled by coupling the ACS terminal to an accumulated charge sinking mechanism.

28. The ACC MOSFET of claim 27, wherein the accumulated charge is removed or otherwise controlled by applying a selected bias voltage V_ACS to the ACS terminal when the ACC MOSFET operates in the accumulated charge regime.

29. The ACC MOSFET of claim 28, wherein the ACC MOSFET comprises a depletion mode NMOSFET device, and wherein V_ACS is selected to be equal to or more negative than the lesser of the source bias voltage and the drain bias voltage.

30. The ACC MOSFET of claim 14, wherein the electrical contact region is positioned a selected distance away from the source, drain and body, thereby reducing parasitic capacitance effects associated with the ACS.

38. The ACC MOSFET of claim 14, wherein when the MOSFET is operated in the accumulated charge regime, the ACS bias voltage (V_ACS) is applied to the ACS to remove the accumulated charge from the MOSFET body via the ACS.

31. A four-terminal accumulated charge control floating body MOSFET (ACC MOSFET) device, adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising:

a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is biased to operate in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer;

b) an accumulated charge sink (ACS) positioned proximate a distal end of the floating body, wherein the ACS is in electrical communication with the floating body; and

c) a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS;

wherein, when the MOSFET is operated in the accumulated charge regime, an ACS bias voltage (V_ACS) is applied to the ACS terminal to control the charge accumulated in the body or to remove the accumulated charge from the body via the ACS terminal.

32. The four-terminal ACC MOSFET of claim 31, wherein the ACS terminal is coupled to an accumulated charge sinking mechanism.

33. The four-terminal ACC MOSFET of claim 32, wherein the accumulated charge sinking mechanism produces a selectable accumulated charge sink bias voltage (V_ACS), and wherein the V_ACS is selected such that the accumulated charge is removed from the body when the ACC MOSFET operates in the accumulated charge regime.

34. The four-terminal ACC MOSFET of claim 33, wherein the accumulated charge sink bias voltage V_ACS is driven by a source having a relatively high impedance.

35. The four-terminal ACC MOSFET of claim 34, wherein the accumulated charge sink bias voltage V_ACS is driven by a source having an impedance greater than approximately 10⁶ ohms.

36. The four-terminal ACC MOSFET of claim 33, wherein the gate, drain and source have associated and respective gate (Vg), drain (Vd) and source (Vs) bias voltages, and wherein the ACS bias voltage V_ACS is selected to be equal to or more negative than the lesser of both Vs and Vd, thereby conveying the accumulated rhetorical charge from the body when the MOSFET operates in the accumulated charge regime.

39. The ACC MOSFET of claim 31, wherein when the MOSFET is operated in the accumulated charge regime, the ACS bias voltage (V_ACS) is applied to the ACS to remove the accumulated charge from the MOSFET body via the ACS terminal.