Wafer level device package with sealing line having electroconductive pattern and method of packaging the same

• US 7,911,043 B2
• Filed: 05/22/2008
• Issued: 03/22/2011
• Est. Priority Date: 05/22/2007
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Hong, Ju Pyo, Ha, Job, Kim, Tae Hoon, Park, Seung Wook, Choi, Seog Moon
• Primary Examiner(s): Dickey; Thomas L
• Assistant Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US12/153,705
• Publication Number:
  US 20080290479A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/666, 257/777, 257/778, 257/E21.51, 257/E23.031, 257/678, 257/730, 257/E33.056, 257/E23.001, 257/E23.061, 438/111, 438/106, 438/113
• US Class Current: 257/678
• CPC Class Codes: B81B 2207/093 Conductive package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H03H 9/1057 for microelectro-mechanical devices
• CPC Class Codes: H03H 9/1071 the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device

Abstract

Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

Claims

1. A wafer level package comprising:

a device substrate comprising a device region, where a device is mounted, on a top surface of the device substrate;

a sealing line comprising a plurality of non-electroconductive patterns and a plurality of electroconductive patterns and forming a side wall to seal the device region; and

a cap substrate comprising a plurality of vias respectively connected to the electroconductive patterns and being attached to a top surface of the sealing line.

2. The wafer level package of claim 1, further comprising a plurality of lead frames disposed on the top surface of the device substrate and connected between the device and the electroconductive patterns of the sealing line.

3. The wafer level package of claim 2, wherein the lead frames do not penetrate the sealing line.

4. The wafer level package of claim 1, wherein an area of the electroconductive patterns is larger than an area of the non-electroconductive patterns.

5. The wafer level package of claim 4, wherein each of the vias penetrates the cap substrate to be connected to one portion of each of the electroconductive patterns.

6. The wafer level package of claim 1, wherein the non-electroconductive patterns are formed of benzocyclobutene (BCB), dry film resin (DFR), epoxy, or thermosetting polymer.

7. The wafer level package of claim 1, wherein the electroconductive patterns are formed of metal or electroconductive paste.

8. A method of packaging a wafer level device, the method comprising:

forming a device and a plurality of connecting patterns electrically connected to the device on a top surface of a first wafer, the first wafer being a device substrate;

forming a sealing line that comprises a plurality of electroconductive patterns connected to the connecting patterns and a plurality of non-electroconductive patterns, the sealing line forming a side wall to seal a device region of the device substrate;

attaching a second wafer, the second wafer being a cap substrate, to a top surface of the sealing line;

forming a plurality of vias in the second wafer, the vias being respectively connected to the electroconductive patterns of the sealing line; and

separating wafer level packages sealing the device, comprising performing a dicing process along the sealing line.

9. The method of claim 8, wherein the forming the plurality of connecting patterns comprises forming a plurality of lead frames.

10. The method of claim 8, wherein the forming of the sealing line comprises forming the non-electroconductive patterns of benzocyclobutene (BCB), dry film resin (DFR), epoxy, or thermosetting polymer using screen printing or injection through a nozzle.

11. The method of claim 8, wherein the forming of the sealing line comprises forming the electroconductive patterns of electroconductive paste using screen printing or injection through a nozzle.

12. The method of claim 8, wherein the forming of the sealing line comprises forming the electroconductive patterns of metal using physical vapor deposition (PVD).

13. The method of claim 8, wherein the performing the dicing process comprises using a scribe line that penetrates the plurality of vias along the sealing line.

14. The method of claim 8, wherein the forming of the vias comprises:

performing an etch process using a photoresist pattern that exposes a portion in contact with the electroconductive patterns so as to form via holes; and

filling the via holes with metal or electroconductive paste.

15. The method of claim 14, wherein the filling the via holes with the metal comprises filling with the metal using physical vapor deposition (PVD) and planarizing the via using a chemical mechanical polishing (CMP) process.

16. The method of claim 14, wherein the filling the via holes with the electroconductive paste comprises filling with the electroconductive paste using screen printing.