Liquid crystal display device and method of driving the same

• US 7,911,431 B2
• Filed: 12/31/2007
• Issued: 03/22/2011
• Est. Priority Date: 01/29/2007
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Jung, Han-Yung
• Primary Examiner(s): LAO, LUNYI
• Application Number:
  US11/968,066
• Publication Number:
  US 20080180380A1
• Time in Patent Office: 1,177 Days
• Field of Search: 345 87-103, 345/204, 345208-210, 345690-691
• US Class Current: 345/89
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/2055 the pattern being varied in time
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A liquid crystal display device includes first to third FRC portions. The first to third FRC portions converts n-bit R, G and B input data into (n−m)-bit R, G and B data having first to third FRC patterns for consecutive P frames according to lower m bits of the n-bit R, G and B input data, respectively. The (n−m)-bit R, G and B data for each of the consecutive P frames correspond to R, G and B sub-pixels of the pixels of the pixel block, respectively.

Claims

1. A liquid crystal display device, comprising:

a liquid crystal panel including a pixel block including pixels, the pixel including R, G and B sub-pixels;

a timing controller that converts an r-bit R external data into an n-bit R input data, converts an r-bit G external data into an n-bit G input data, and converts an r-bit B external data into an n-bit B input data if the r does not equal the n, wherein the timing controller converts the r-bit R, G and B external data into the respective R, G and B n-bit input data by adding a lowermost bit having a value zero to the respective r-bit R, G and B external data;

a first FRC portion that converts the n-bit R input data into (n−

m)-bit R data having a first FRC pattern for consecutive P frames according to lower m bits of the n-bit R input data, wherein the (n−

m)-bit R data for each of the consecutive P frames correspond to the R sub-pixels of the pixels of the pixel block, respectively;

a second FRC portion that converts the n-bit G input data into (n−

m)-bit G data having a second FRC pattern for the consecutive P frames according to lower m bits of the n-bit G input data, wherein the (n−

m)-bit G data for each of the consecutive P frames correspond to the G sub-pixels of the pixels of the pixel block, respectively; and

a third FRC portion that converts the n-bit B input data into (n−

m)-bit B data having a third FRC pattern for the consecutive P frames according to lower m bits of the n-bit B input data, wherein the (n−

m)-bit B data for each of the consecutive P frames correspond to the B sub-pixels of the pixels of the pixel block, respectively,

wherein the first, second and third FRC patterns are different and correspond to the R, G and B sub-pixels, respectively, and

wherein the P,r,n and m are natural numbers, the r is less than or equal to the n, and the n is greater than the m.

2. The device of claim 1, wherein the P are 2^m.

3. The device of claim 1, wherein the n is 9 and the m is 3.

4. The device of claim 1, wherein the pixel block includes the pixels in a K×

l matrix, and wherein the K is greater than 1 and the L is greater than 1.

5. The device of claim 1, wherein each of the (n−

m)-bit R, G and B data has one of a gray level represented by upper (n−

m) bits of each of the n-bit R, G and B input data and a next higher gray level.

6. A method of driving a liquid crystal display device, comprising:

converting an r-bit R external data into an n-bit R input data, an r-bit G external data into an n-bit G input data, and an r-bit B external data into an n-bit B input data if the r does not equal the n, wherein converting the r-bit R, G and B external data into the respective R, G and B n-bit input data comprises adding a lowermost bit having a value zero to the respective r-bit R, G and B external data;

converting the n-bit R input data into (n−

m)-bit R data having a first FRC pattern for consecutive P frames according to lower m bits of the n-bit R input data;

converting the n-bit G input data into (n−

m)-bit G data having a second FRC pattern for the consecutive P frames according to lower m bits of the n-bit G input data;

converting the n-bit B input data into (n−

m)-bit B data having a third FRC pattern for the consecutive P frames according to lower m bits of the n-bit B input data; and

displaying images through a liquid crystal panel including a pixel block including pixels, the pixel including R, G and B sub-pixels,

wherein the (n−

m)-bit R data for each of the consecutive P frames correspond to the R sub-pixels of the pixels of the pixel block, respectively, wherein the (n−

m)-bit G data for each of the consecutive P frames correspond to the G sub-pixels of the pixels of the pixel block, respectively, wherein the (n−

m)-bit B data for each of the consecutive P frames correspond to the B sub-pixels of the pixels of the pixel block, respectively, wherein the first to third FRC pattern are different and correspond to the R, G and B sub-pixels, respectively, and wherein the P, r, n and m are natural number, the r is less than or equal to the n, and the n is greater than the m.

7. The method of claim 6, wherein the P are 2^m.

8. The method of claim 6, wherein the n is 9 and the m is 3.

9. The method of claim 6, wherein the pixel block includes the pixels in a K×

L matrix, and wherein the K is greater than 1 and the L is greater than 1.

10. The method of claim 6, wherein each of the (n−

m)-bit R, G and B data has one of a gray level represented by upper (n−

n) bits of each of the n-bit R, G and B input data and a next higher gray level.