Path maintenance mechanism

• US 7,917,672 B2
• Filed: 03/31/2009
• Issued: 03/29/2011
• Est. Priority Date: 05/18/2006
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Aoki, Makoto, Komatsu, Yuki
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US12/415,346
• Publication Number:
  US 20090204733A1
• Time in Patent Office: 728 Days
• Field of Search: 710/38
• US Class Current: 710/38
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: H04L 45/02 Topology update or discovery

Abstract

In the computer system including a host computer and a storage system, the storage system includes a physical disk and a disk controller, and provides a storage area of the physical disk as at least one logical unit. The processor obtains, at a first time point and a second time point different from the first time point, a relation between a logical path and a component through which the logical path passes, stores, as logical path connection information, the relations obtained at the first time point and the second time point, refers to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other, and specifies the logical path which does not exist at the second time point among the logical paths existing at the first time point.

A1

Claims

1. A computer system, comprising:

at least one host computer including a processor, a memory, a display and an interface; and

at least one storage system coupled to the host computer,

wherein the storage system comprises a physical disk which stores data requested to be written by the host computer and a disk controller which controls the physical disk, and provides the host computer with a storage area of the physical disk as at least one logical unit,

wherein the processor obtains, at a first time point and a second time point different from the first time point, a relation between a logical path serving as an access route from the host computer to the logical unit and at least one component through which the logical path passes,

wherein the processor stores the relations obtained at the first time point and the second time point,

wherein the processor displays on the display logical path connection information including a Path ID, an identifier of said logical unit, said at least one component through which the logical path passes and an Identical Path ID for each said logical path from the relations obtained at the first time point and the second time point to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other, and

wherein the processor specifies on the display the logical paths existing at the second time point that differ from the logical paths existing at the first time point.