Current-controlled CMOS circuits with inductive broadbanding

• US 7,919,985 B2
• Filed: 02/10/2009
• Issued: 04/05/2011
• Est. Priority Date: 02/24/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Green, Michael M.
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US12/368,934
• Publication Number:
  US 20090140771A1
• Time in Patent Office: 784 Days
• Field of Search: 326/83, 326 86- 88, 326/112, 326/115, 326/119, 326/121, 327/50, 327/52, 327/65, 327/81, 327/89
• US Class Current: 326/83
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2203/45506 the CSC comprising only one switch
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45704 the LC comprising one or more parallel resonance circuits
• CPC Class Codes: H03F 2203/7203 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias current in the amplifier
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C³MOS logic with inductive broadbanding/C³MOS logic with low power conventional CMOS logic. The combined C³MOS logic with inductive broadbanding/C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus, comprising:

a deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic with inductive broadbanding, that converts a differential input signal into a plurality of signals, wherein;

the deserializer circuit block is implemented using a first n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second n-channel MOSFET having their source terminals coupled, their gate terminals coupled respectively to receive the differential input signal, and their drain terminals coupled respectively to first and second output nodes; and

the deserializer circuit block includes;

a first impedance, having a first resistance and a first inductance, coupled between the first output node and a logic high level;

a second impedance, having a second resistance and a second inductance, coupled between the second output node and the logic high level; and

a current-source n-channel MOSFET coupled between the coupled source terminals of the first and second n-channel MOSFETs and a logic low level.

2. The apparatus of claim 1, further comprising:

first and second capacitive loads coupled respectively to the first and second output nodes.

3. The apparatus of claim 1, wherein:

the first inductance is a first spiral inductor; and

the second inductance is a second spiral inductor.

4. The apparatus of claim 1, wherein:

the first inductance is a first active inductor implemented using at least a first transistor; and

the second inductance is a second active inductor implemented using at least a second transistor.

5. The apparatus of claim 1, wherein:

the differential input signal has a first frequency; and

each of the plurality of signals has a second frequency.

6. The apparatus of claim 5, wherein:

the second frequency is less than the first frequency.

7. The apparatus of claim 5, wherein:

the first frequency is an integer multiple of the second frequency.

8. The apparatus of claim 1, further comprising:

a processing circuit block, coupled to the deserializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that generates a plurality of processed signals.

9. The apparatus of claim 8, wherein:

the deserializer circuit block and the processing circuit block are both implemented on a single silicon die.

10. The apparatus of claim 8, wherein:

the differential input signal has a first frequency;

each of the plurality of signals has a second frequency; and

each of the plurality of processed signals has the second frequency.

11. The apparatus of claim 10, wherein:

the second frequency is less than the first frequency.

12. The apparatus of claim 10, wherein:

the first frequency is an integer multiple of the second frequency.

13. The apparatus of claim 1, further comprising:

at least one additional deserializer circuit block, implemented in a parallel configuration with respect to the deserializer circuit block and implemented using C³MOS logic with inductive broadbanding, that converts at least one additional differential input signal into at least one additional plurality of signals; and

wherein;

the deserializer circuit block and the at least one additional deserializer circuit block compose a multi-channel serial link circuit; and

the deserializer circuit block and the at least one additional deserializer circuit block are both implemented on a single silicon die.

14. The apparatus of claim 1, further comprising:

at least one additional deserializer circuit block, implemented using C³MOS logic with inductive broadbanding, that converts at least one additional differential input signal into at least one additional plurality of signals; and

wherein;

the deserializer circuit block and the at least one additional deserializer circuit block are both implemented on a single silicon die.

15. An apparatus, comprising:

a serializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic with inductive broadbanding, that converts a plurality of signals into a serialized signal, wherein;

the serializer circuit block is implemented using a first n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second n-channel MOSFET having their source terminals coupled, their gate terminals coupled respectively to receive a differential input signal corresponding to at least one of the plurality of signals, and their drain terminals coupled respectively to first and second output nodes; and

the serializer circuit block includes;

a first impedance, having a first resistance and a first inductance, coupled between the first output node and a logic high level;

a second impedance, having a second resistance and a second inductance, coupled between the second output node and the logic high level; and

a current-source n-channel MOSFET coupled between the coupled source terminals of the first and second n-channel MOSFETs and a logic low level.

16. The apparatus of claim 15, further comprising:

first and second capacitive loads coupled respectively to the first and second output nodes.

17. The apparatus of claim 15, wherein:

the first inductance is a first spiral inductor; and

the second inductance is a second spiral inductor.

18. The apparatus of claim 15, wherein:

the first inductance is a first active inductor implemented using at least a first transistor; and

the second inductance is a second active inductor implemented using at least a second transistor.

19. The apparatus of claim 15, wherein:

each of the plurality of signals has a first frequency; and

the serialized signal has a second frequency.

20. The apparatus of claim 19, wherein:

the second frequency is greater than the first frequency.

21. The apparatus of claim 19, wherein:

the second frequency is an integer multiple of the first frequency.

22. The apparatus of claim 15, further comprising:

a processing circuit block, coupled to the serializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that generates the plurality of signals.

23. The apparatus of claim 22, wherein:

the serializer circuit block and the processing circuit block are both implemented on a single silicon die.

24. The apparatus of claim 22, wherein:

each of the plurality of signals has a first frequency; and

the serialized signal has a second frequency.

25. The apparatus of claim 24, wherein:

the second frequency is greater than the first frequency.

26. The apparatus of claim 24, wherein:

the second frequency is an integer multiple of the first frequency.

27. The apparatus of claim 15, further comprising:

at least one additional serializer circuit block, implemented in a parallel configuration with respect to the serializer circuit block and implemented using C³MOS logic with inductive broadbanding, that converts at least one additional plurality of signals into at least one additional serialized signal; and

wherein;

the serializer circuit block and the at least one additional serializer circuit block compose a multi-channel serial link circuit; and

the serializer circuit block and the at least one additional serializer circuit block are both implemented on a single silicon die.

28. The apparatus of claim 15, further comprising:

at least one additional serializer circuit block, implemented using C³MOS logic with inductive broadbanding, that converts at least one additional plurality of signals into at least one additional serialized signal; and

wherein;

the serializer circuit block and the at least one additional serializer circuit block are both implemented on a single silicon die.

29. An apparatus, comprising:

a deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic with inductive broadbanding, that converts a differential input signal into a plurality of signals, wherein;

the deserializer circuit block is implemented using a first n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second n-channel MOSFET having their source terminals coupled, their gate terminals coupled respectively to receive the differential input signal, and their drain terminals coupled respectively to first and second output nodes; and

the deserializer circuit block includes;

a first impedance, having a first resistance and a first inductance, coupled between the first output node and a logic high level;

a second impedance, having a second resistance and a second inductance, coupled between the second output node and the logic high level; and

a current-source n-channel MOSFET coupled between the coupled source terminals of the first and second n-channel MOSFETs and a logic low level.

a processing circuit block, coupled to the deserializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that generates a plurality of processed signals; and

a serializer circuit block, implemented C³MOS logic, that converts at least a portion of the plurality of processed signals into a serialized signal.

30. The apparatus of claim 29, wherein:

the serializer circuit block is implemented using C³MOS logic with inductive broadbanding, wherein;

the serializer circuit block is implemented using a third n-channel MOSFET and a fourth n-channel MOSFET having their source terminals coupled, their gate terminals coupled respectively to receive a differential input signal corresponding to at least one of the plurality of processed signals, and their drain terminals coupled respectively to third and fourth output nodes; and

the serializer circuit block includes;

a third impedance, having a third resistance and a third inductance, coupled between the third output node and the logic high level;

a fourth impedance, having a fourth resistance and a fourth inductance, coupled between the fourth output node and the logic high level; and

at least one additional current-source n-channel MOSFET coupled between the coupled source terminals of the third and fourth n-channel MOSFETs and the logic low level.

31. The apparatus of claim 29, further comprising:

first and second capacitive loads coupled respectively to the first and second output nodes.

32. The apparatus of claim 29, wherein:

the first inductance is a first spiral inductor; and

the second inductance is a second spiral inductor.

33. The apparatus of claim 29, wherein:

the first inductance is a first active inductor implemented using at least a first transistor; and

the second inductance is a second active inductor implemented using at least a second transistor.

34. The apparatus of claim 29, wherein:

the differential input signal has a first frequency;

each of the plurality of signals has a second frequency;

each of the plurality of processed signals has the second frequency; and

the serialized signal has a third frequency.

35. The apparatus of claim 34, wherein:

the first frequency is the third frequency.

36. The apparatus of claim 34, wherein:

the second frequency is less than the first frequency.

37. The apparatus of claim 34, wherein:

the first frequency is an integer multiple of the second frequency.

38. The apparatus of claim 29, wherein:

the deserializer circuit block, the processing circuit block, and the serializer circuit block are all implemented on a single silicon die.