Calibration methods and circuits to calibrate drive current and termination impedance

• US 7,928,757 B2
• Filed: 06/21/2010
• Issued: 04/19/2011
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Lau, Benedict, Nguyen, Huy M., Gadde, Vijay
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US12/819,939
• Publication Number:
  US 20100259295A1
• Time in Patent Office: 302 Days
• Field of Search: 326/30, 326 26- 27
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 21/08 Output circuits
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Claims

1. An integrated circuit device comprising:

a receiver circuit including a differential amplifier to receive a pair of complementary input signals via respective first and second nodes;

a first termination element, exhibiting a first impedance, coupled to the first node;

a second termination element, exhibiting a second impedance, coupled to the second node; and

a control circuit to set a termination value for each of the first and second termination elements, the control circuit comprising;

a digitally adjustable termination element exhibiting a third impedance;

a comparator having first and second inputs, the first input to receive a reference voltage and the second input to receive a voltage developed by drawing a first current through the digitally adjustable termination element; and

a first counter circuit to provide a first digital value that is updated based on an output of the comparator, wherein the first digital value is used to set the first, second, and third impedances.

2. The integrated circuit device of claim 1, wherein the control circuit further includes a current source to draw the first current through the digitally adjustable termination element.

3. The integrated circuit device of claim 1, further comprising a pad to couple to a reference resistor external to the integrated circuit device and a current source to draw a second current through the reference resistor to develop the reference voltage.

4. The integrated circuit device of claim 3, wherein the current source comprises a first transistor to draw the second current based on a bias voltage and a second transistor to receive the bias voltage and draw the first current through the digitally adjustable termination element.

5. The integrated circuit device of claim 3, further comprising:

a pad to couple to an external reference voltage; and

a multiplexer to selectively provide the external reference voltage to the second input of the comparator, such that the comparator compares the reference voltage received at the first input to the external reference voltage and establishes the second current based on the comparison.

6. The integrated circuit device of claim 1, the control circuit further comprising a sampling latch to capture the output of the comparator, wherein the counter circuit updates the first digital value based on the captured output.

7. The integrated circuit device of claim 1, wherein the digitally adjustable termination element includes parallel resistive paths.

8. The integrated circuit device of claim 7, wherein the parallel resistive paths include transistors to selectively enable ones of the resistive paths in response to the digital value.

9. The integrated circuit device of claim 8, wherein the transistors comprise PMOS transistors.

10. The integrated circuit device of claim 8, wherein the parallel resistive paths provide binary-weighted resistances for the third impedance.

11. The integrated circuit device of claim 1, further comprising a transmitter circuit to transmit a pair of complementary output signals via the respective first and second nodes.

12. The integrated circuit device of claim 11, further comprising a second counter circuit to provide a second digital value that is updated based on an output of the comparator, wherein the second digital value is used to set a drive current of the transmitter.

13. The integrated circuit device of claim 12, further comprising a multiplexer coupled to the second input of the comparator, wherein the voltage developed by drawing the first current through the digitally adjustable termination element is selectively applied to the second input of the comparator via the multiplexer.

14. The integrated circuit of claim 13, further comprising a current source to draw the first current through the digitally adjustable termination element, wherein the multiplexer selectively applies a second reference voltage to the second input of the comparator to set the first current.

15. The integrated circuit of claim 14, wherein the multiplexer applies the second reference voltage to the second input of the comparator to update the second digital value, wherein the first current is set based on the second digital value.

16. A method for terminating a differential signal channel, the method comprising:

receiving first and second complementary input signals at respective first and second pads;

terminating the first and second pads of the differential signal channel with respective first and second termination elements exhibiting respective first and second termination impedances;

drawing a current through a digitally adjustable reference resistor to obtain a reference-resistor voltage;

comparing the reference-resistor voltage with a reference voltage;

updating a digital value stored in a counter based on the comparing; and

adjusting the digitally adjustable reference resistor and the first and second termination impedances in response to the digital value.

17. The method of claim 16, wherein drawing a current through the digitally adjustable reference resistor comprises drawing the current through a current source.

18. The method of claim 16, further comprising drawing a second current through an external reference resistor to obtain the reference-resistor voltage.

19. The method of claim 18, wherein adjusting the digitally adjustable termination element includes selectively enabling parallel resistive paths.

20. The method of claim 19, wherein the parallel resistive paths support binary-weighted resistances.

21. The method of claim 16, further comprising transmitting a differential signal on the first and second pads using a predetermined voltage swing.

22. The method of claim 21, further comprising:

comparing an external reference voltage with the reference voltage;

updating a second digital value stored in a second counter based on comparing the external reference voltage with the reference voltage; and

adjusting the predetermined voltage swing based on the second digital value.

23. An integrated circuit device comprising:

a plurality of receiver circuits, each receiver circuit of the plurality of receiver circuits including;

a differential amplifier to receive a pair of complementary input signals via respective first and second input nodes;

a first termination element, exhibiting a first impedance, coupled to the respective first input node of each receiver circuit; and

a second termination element, exhibiting a second impedance, coupled to the respective second input node of each receiver circuit; and

a control circuit to set a termination value for each of the first and second termination elements, the control circuit comprising;

a digitally adjustable termination element exhibiting a third impedance;

a comparator having first and second inputs, the first input to receive a reference voltage and the second input to receive a second voltage developed by drawing a current through the digitally adjustable termination element; and

a counter circuit to provide a digital value that is updated based on an output of the comparator, wherein the digital value is used to set the first and second impedances of each respective receiver circuit, and the third impedance.

24. The integrated circuit device of claim 23, the control circuit further comprising a sampling latch to capture the output of the comparator, wherein the counter circuit updates the digital value based on the captured output.

25. The integrated circuit device of claim 23, wherein the digitally adjustable termination element includes parallel resistive paths.

26. The integrated circuit device of claim 25, wherein the parallel resistive paths include transistors to selectively enable ones of the resistive paths in response to the digital value.

27. The integrated circuit device of claim 26, wherein the transistors comprise PMOS transistors.

28. The integrated circuit device of claim 26, wherein the parallel resistive paths provide binary-weighted resistances for the third impedance.