Wiring structure and wiring designing method

• US 7,935,630 B2
• Filed: 01/11/2008
• Issued: 05/03/2011
• Est. Priority Date: 01/12/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Sato, Motonobu
• Primary Examiner(s): Brewster; William M
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US11/972,944
• Publication Number:
  US 20080179084A1
• Time in Patent Office: 1,208 Days
• Field of Search: 257/208, 257/758, 257/773, 438/666, 438/669, 438/468, 438/957, 438/761
• US Class Current: 438/666
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

A designing method of a semiconductor device having a first wire and a second wire with a plurality of vias includes determining a first life time change rate of the semiconductor device in response to a change in a number of via column, a second life time change rate of the semiconductor device in response to a change in a number of via row, reducing the number of via column according to a ratio based on the first life time change and the second life time change; and increasing the number of via row at least one.

Claims

1. A designing method of a semiconductor device including a first wire and a second wire with a plurality of vias, comprising:

determining a first life time change rate of the first or the second wire in response to a change in a number of via in column direction arranged in a wire-width direction;

determining a second life time change rate of the first or the second wire in response to a change in a number of via in row direction arranged in a wire-length direction;

reducing the number of via in column according to a ratio “

N”

based on the first life time change rate and the second life time change rate, wherein the ratio “

N”

is represented as the ratio “

N”

=(the second life time changes rate)/(the first life time changes rate);

where, ratio “

N”

is an integer obtained by discarding the fractional part; and

increasing the number of via in row at least one.

2. The designing method according to claim 1, wherein, when the first life time change rate of the wire is represented by S_column and the second life time change rate of the wire is represented by S_line, a life time of the semiconductor is represented as

the life time ∝

exp(S_column×

the number of via in column) and

the life time ∝

exp(S_line×

the number of via in row).

3. The designing method according to claim 1, further comprising:

increasing the number of via in row or the number of via in column by one as long as the total number of vias does not exceed the total number of vias before the steps of increasing the number of via in row direction and decreasing the number of via in column direction are performed.

4. The designing method according to claim 1, wherein the number of via column is reduced by ratio “

N”

every time the number of via in row is increased by one.

5. The designing method according to claim 1, wherein the number of via in column is set to one if the original number of via in column is not greater than ratio “

N”

.

6. The designing method according to claim 1, wherein increasing the number of via in row and decreasing the number of via in column are repeatedly performed to reduce the number of via in column ultimately to one.

7. The designing method according to claim 1, wherein greater current allowed for the vias is set as width of the first wire and the second wires becomes wider.

8. The designing method according to claim 2, wherein greater current allowed for the vias is set as width of the first wire and the second wires becomes wider.

9. The designing method according to claim 3, wherein greater current allowed for the vias is set as width of the first wire and the second wires becomes wider.

10. The designing method according to claim 4, wherein greater current allowed for the vias is set as width of the first wire and the second wires becomes wider.

11. The designing method according to claim 5, wherein greater current allowed for the vias is set as width of the first wire and the second wires becomes wider.

12. The designing method according to claim 6, wherein greater current allowed for the vias is set as width of the first wire and the second wires becomes wider.

13. A designing method of a semiconductor device including a first wire and a second wire with a plurality of vias, the second wire being located on a layer different from that of the first wire and extending in a diagonal or orthogonal direction with respect to the first wire, the method comprising:

arranging the plurality of vias, in a line to be parallel to one of the first wire and the second wire that is located on an electron-flow downstream side with respect to the vias.

14. The designing method according to claim 13, wherein the plurality of vias are arranged, in a line, along both of the first wire and the second wire if electrons flow in both directions through the first wire and the second wire.