Reference oscillator and its use

• US 7,936,227 B2
• Filed: 05/30/2008
• Issued: 05/03/2011
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Hitachi, Ltd., Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Young, Phil
• Primary Examiner(s): Kinkead; Arnold
• Assistant Examiner(s): Tan; Richard
• Application Number:
  US12/130,271
• Publication Number:
  US 20080303601A1
• Time in Patent Office: 1,068 Days
• Field of Search: 331/66, 331/116.R, 331/154, 331/158, 331/175, 331/176, 331/177.R
• US Class Current: 331/158
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/35 Constructional details or hardware or software details of the signal processing chain
• CPC Class Codes: H03L 1/028 of generators comprising piezoelectric resonators H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32

Abstract

A reference clock circuit (170), has a low-power mode, in which the frequency consumption is reduced, and including an internal counter, accumulating time spent in low-power mode. The circuit includes a crystal resonator (60), an oscillator circuit (70), and a temperature compensation circuit (80), providing a stable clock output (85). During low-power mode temperature compensation can be switched off. The circuit further provides a wakeup signal (107) after a preset time in low-power mode.

Claims

1. A reference oscillator circuit comprising:

a command input to carry a control logic signal setting a normal-running mode and a low-power mode;

a crystal resonator;

an oscillator coupled to the crystal resonator, the oscillator for providing a temperature-compensated clock output signal;

a temperature compensation circuit coupled to the oscillator;

a logic element coupled to the command input and to the oscillator, wherein the logic element produces a clock pulse based on a signal from the oscillator when in the low-power mode and disables the clock pulse when in the normal-running mode; and

a counter coupled to the logic element to receive the clock pulse and to provide a count of clock pulses based on being in the low-power mode.

2. The reference oscillator circuit of claim 1, wherein the oscillator is further coupled to the command input, and wherein the oscillator produces a first frequency when in the normal-running mode and a second frequency when in the low-power mode.

3. The reference oscillator circuit of claim 1, wherein the control logic signal enables the temperature compensation circuit when in the normal-running mode and disables the temperature compensation circuit when in the low-power mode.

4. The reference oscillator circuit of claim 1, wherein the control logic signal enables the temperature compensation circuit when in the normal-running mode and operates the temperature compensation circuit intermittently when in the low-power mode.

5. The reference oscillator circuit of claim 1, wherein the counter is further coupled to the command input and configured to reset the counter when entering the low-power mode.

6. The reference oscillator circuit of claim 1, wherein the counter is further coupled to the command input and configured to stop counting when in the normal-running mode.

7. The reference oscillator circuit of claim 1, wherein the counter comprises an externally accessible counter output interface.

8. The reference oscillator circuit of claim 1, wherein the control logic signal disables the oscillator from providing the temperature-compensated clock output signal when in the low-power mode.

9. The reference oscillator circuit of claim 1, wherein the logic element comprises a divider.

10. The reference oscillator circuit of claim 1, further comprising a comparator coupled to the counter and configured provide a wakeup signal when the count of clock pulses reaches a preset value.

11. A method of providing a temperature-compensated clock output signal from a reference oscillator circuit, the method comprising:

accepting a control logic signal from a command input, wherein the control logic signal sets a normal-running mode and a low-power mode;

disabling a logic element from producing a dock pulse when entering the normal-running mode;

providing the temperature-compensated clock output signal from an oscillator coupled to a crystal resonator and a temperature compensation circuit when in the normal-running mode;

providing clock pulses from the logic element to a counter to count based on being in the low-power mode; and

counting based on the clock pulse from the logic element when in the low-power mode.

12. The method of claim 11, further comprising:

producing a first frequency for the temperature-compensated clock output signal when in the normal-running mode; and

producing a second frequency when in the low-power mode.

13. The method of claim 11, further comprising:

enabling the temperature-compensated circuit when in the normal-running mode; and

disabling the temperature-compensated circuit when in the low-power mode.

14. The method of claim 11, further comprising:

enabling the temperature-compensated circuit when in the normal-running mode; and

operating the temperature-compensated circuit intermittently when in the low-power mode.

15. The method of claim 11, further comprising resetting the counter when entering the low-power mode.

16. The method of claim 11, further comprising disabling the counter when entering the normal-running mode.

17. The method of claim 11, further comprising providing an externally accessible counter output from the counter.

18. The method of claim 11, further comprising disabling the oscillator from providing the temperature-compensated clock output signal when in the low-power mode.

19. The method of claim 11, wherein the act of providing clock pulses from the logic element comprises providing the clock pulses from a divider.

20. The method of claim 11, further comprising providing a wakeup signal from a comparator when the counting reaches a preset value.