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External memory controller node

  • US 7,937,538 B2
  • Filed: 05/07/2009
  • Issued: 05/03/2011
  • Est. Priority Date: 11/22/2002
  • Status: Active Grant
First Claim
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1. A computing machine embodied in an integrated circuit comprising:

  • a memory interface coupled to an external memory;

    a plurality of heterogeneous computational nodes configured to make memory requests for accesses to the external memory; and

    a memory controller including ports that have parameters, the memory controller configured to generate memory locations for the memory requests based on the parameters and to allow accesses by the heterogeneous computational nodes to the external memory at the memory locations in response to the memory requests.

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