Memory array error correction apparatus, systems, and methods
First Claim
1. An apparatus comprising:
- a memory array; and
an error code module coupled to the memory array and including a data buffer having a plurality of data registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, the error code module operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles,wherein the error code module is further operable to interleave operations of the read/modify/write processes such that read and write operations do not occur simultaneously.
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Accused Products
Abstract
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
18 Citations
48 Claims
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1. An apparatus comprising:
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a memory array; and an error code module coupled to the memory array and including a data buffer having a plurality of data registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, the error code module operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles, wherein the error code module is further operable to interleave operations of the read/modify/write processes such that read and write operations do not occur simultaneously. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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receiving a plurality of data bursts to be written to a memory array on a corresponding plurality of consecutive clock cycles; and performing a read/modify/write process for each of the plurality of data bursts within a time period no longer than a period of two cycles of the corresponding plurality of consecutive clock cycles, wherein each of the read/modify/write processes includes a read operation, a modify operation, and a write operation, and read operations and write operations do not occur simultaneously. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method comprising:
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receiving a first plurality of input bits and a first address reading at the first address a first group of stored data bits to generate a first group of read data bits responsive to a first clock cycle transition; receiving a second group of input bits and a second address; generating a first group of write data bits by combining the first plurality of input bits with the first group of read data bits; reading at the second address a second group of stored data bits to generate a second group of read data bits responsive to a second clock cycle transition; generating a second group of write data bits by combining the second plurality of input bits with the first group of read data bits; and after reading at the second address, writing the first group of write data bits to the first address before a third clock cycle transition, wherein said reading at the first address and said writing do not occur simultaneously, and said reading at the second address and said writing do not occur simultaneously. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method comprising:
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providing a first data burst during a first clock cycle and providing a second data burst during a second and consecutive clock cycle; and within a time period no longer than an interval defined by the first clock cycle and the second clock cycle; receiving a first plurality of data bits corresponding to the first data burst; receiving a second plurality of data bits corresponding to the second data burst; combining the first data burst and the first plurality of data bits to generate a plurality of write data bits; after combining, storing the plurality of write data bits; after storing, generating a plurality of error correction code bits associated with the plurality of write data bits; and writing the plurality of write data bits and the plurality of error correction code bits to an array of memory cells. - View Dependent Claims (32, 33, 34)
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35. A system comprising:
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a processor coupled to a memory array, the processor operable to provide a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, and a data mask for each of the plurality of data bursts; and an error code module coupled to the processor and to the memory array, the error code module operable to receive the plurality of data bursts and to perform a read/modify/write process for each of the plurality of data bursts within a time period no longer than a period of two cycles of the plurality of consecutive clock cycles, wherein the error code module is further operable to interleave operations of the read/modify/write processes such that read and write operations do not occur simultaneously. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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Specification