Heads-up-display software development tool for analyzing and optimizing computer software

• US 7,950,003 B1
• Filed: 03/02/2007
• Issued: 05/24/2011
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Peterson, Stace, Stamate, Vlad, Flynn, Thomas, Duca, Nathaniel G., De Pereyra, Alexandre
• Primary Examiner(s): Khatri; Anil
• Application Number:
  US11/681,629
• Time in Patent Office: 1,544 Days
• Field of Search: 717124-129, 717/131, 717/151, 717141-144
• US Class Current: 717/124
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 11/3612 by runtime analysis performance monitoring G06F11/3466
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 8/20 Software design

Abstract

A method and apparatus for software development and a method and system for analysis of graphics software are disclosed.

Claims

1. A system for analysis of graphics software, comprising

a central processing unit (CPU);

a graphics processing (GPU) unit coupled to the CPU;

a memory coupled to the GPU and CPU, the memory having therein a command buffer and a push buffer;

a graphics program configured to run on the CPU, wherein the graphics program places commands in the command buffer for a graphics processor unit (GPU)

a graphics program analysis program running on the CPU, wherein the graphics analysis (HUD) program includes one or more instructions comprising;

a) one or more instructions that when executed by the CPU copies a program chunk from the command buffer to a push buffer, wherein the program chunk is configured to be executed by the GPU from the push buffer; and

b) one or more instructions that when executed by the CPU modify the program chunk before the program chunk is executed by the GPU from the push buffer through command buffer and/or push buffer manipulation that is transparent to the graphics program; and

c) one or more instructions that, when executed by the CPU, implement a function on a source of the program chunk, wherein the function facilitates analysis of the graphics program.

2. The system of claim 1 wherein b) comprises one or more instructions that, when executed by the CPU, implement a function on a source of the program chunk, wherein the function facilitates analysis of the graphics program.

3. The system of claim 2, wherein the HUD program further comprises, one or more instructions that, when executed by the CPU, determine a processing time on the graphics processor associated with handling of the program chunk and subtract the processing time when computing timing of processing the program chunk with the graphics processor.

4. The system of claim 1 wherein b) comprises one or more instructions that, when executed by the CPU, apply one or more filters to the program chunk.

5. The system of claim 1 wherein the one or more filters are chosen from the group of a Simple Shader, a 1×

1 Viewport, a Register Count, a Disable Render, a Reduce Geometry, a Disable ZCULL, a 1×

1 Textures and a Wait For Idle filter.

6. The system of claim 1, wherein b) comprises one or more save instructions that, when executed by the CPU, save frame data associated with a frame drawn by the GPU.

7. The system of claim 6 wherein the one or more save instructions comprise:

i) one or more instructions that, when executed by the CPU, save an initial set of frame data for an initial draw call, wherein the frame data is made up of two or more portions;

ii) one or more instructions that, when executed by the CPU, determine for a subsequent draw which, if any, of the two more portions has been changed by the subsequent draw call; and

iii) one or more instructions that, when executed by the CPU, save those portions which have been changed by the subsequent draw call.

8. The system of claim 7 wherein ii) comprises computing an initial hash function for each of the two or more portions of the initial frame data;

computing a subsequent hash function for one or more of the portions after the subsequent draw call; and

comparing the initial and subsequent hash functions.

9. The system of claim 8 wherein ii) further comprises estimating whether one or more portions are used by the subsequent draw call;

and hashing a given portion only if it is estimated that the given portion has been used by the subsequent draw call.

10. The system of claim 1 wherein b) comprises one or more instructions that, when executed by the CPU, implement a shader debugger.

11. The system of claim 10 wherein the shader debugger comprises one or more instructions that, when executed by the CPU insert a shader debug sequence F(D) into the push buffer between a state chunk S and a draw call D, wherein the debug sequence includes a placeholder D′

for the draw call D, a state modifier portion that modifies the state from a state defined by the state chunk S, and a revert instruction REV that reverts state to that associated with the state chunk S.

12. The system of claim 11 wherein the placeholder D′

includes a jump instruction JMP that causes the GPU to jump to a wait instruction that causes the GPU to wait until the draw call D has been copied to a memory location reserved for draw call D.

13. The system of claim 12, wherein the shader debugger further comprises:

one or more instructions that, when executed by the GPU, copy the draw call D from the command buffer to the memory location reserved for the draw call D and either (a) copy the draw call D to the push buffer or (b) execute draw call D from the memory location with the GPU; and

a revert command REV that, when executed by the GPU reverts a state and execute the draw call D again from the push buffer with the GPU.

14. The system of claim 13 wherein the state modifier portion comprises a bind new shader instruction BNS, a bind surface instruction BS, a placeholder D′

for the draw call D and wherein the revert command REV is configured to undo the BNS and BS commands when executed by the GPU.

15. The system of claim 1 wherein the CPU comprises a cell processor having a power processor element and one or more synergistic processor elements.

16. The system of claim 1 wherein b) comprises:

i) one or more instructions that, when executed by the CPU, insert a front command immediately before the program chunk in the push buffer, wherein the front command changes the operation of the program chunk in a way that facilitates analysis of the graphics program;

ii) one or more instructions that, when executed by the CPU, move a get to a point before a beginning of the front command in the push buffer;

iii) one or more instructions that, when executed by the CPU, insert a back command immediately after the program chunk, wherein the back command is configured to revert a configuration of the program to a configuration it would have had without the front command;

iv) one or more instructions that, when executed by the CPU, move a put in the push buffer to a point after an end of the back command.

17. The system of claim 16, further comprising v) one or more instructions that, when executed by the CPU, place time stamps immediately before and after the program chunk.

18. The system of claim 17, wherein the HUD program further comprises one or more instructions that, when executed by the CPU, determine a time utilized by the graphics processor in executing the front and back commands using the time stamps and subtracting the time when computing timing of processing of the program chunk with the graphics processor.

19. The system of claim 16 wherein the front command and/or back command is configured to implement a function on the program chunk.

20. The system of claim 16, wherein the front command and/or back command implements a function on the program chunk, wherein the function requires information from a memory that is not yet available when the front or back command is put in the push buffer, the HUD program further comprising;

a) one or more instructions that, when executed by the CPU, prevent execution of the front command, program chunk or back command until the information is available;

b) one or more instructions that, when executed by the CPU, import the information to the function once the information becomes available; and

c) one or more instructions that, when executed by the CPU, subsequently permit execution of the front command, program chunk or back command.

21. The system of claim 20 wherein the function is part of a vertex driver, shader debug driver, shader defrag disassembly driver filter or driver that asks for data that was in memory at a time of a draw call.

22. The system of claim 16, wherein the program chunk comprises one or more commands that set a state associated with a subsequent draw command.

23. The system of claim 22 wherein the front command is configured to modify the state from an initial value and the back command reverts the state to the initial value.