Time delay apparatus
First Claim
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1. A time delay apparatus for generating a plurality of phase shifted signals comprising:
- a phase locked loop generating a phase control signal, the phase locked loop comprisinga voltage controlled oscillator that generates a first clock signal;
a frequency divider for dividing the first clock signal;
receiving means for receiving a second clock signal; and
a phase comparator for comparing a phase difference between an output of the frequency divider and the second clock signal to produce the phase control signal;
wherein;
the phase control signal specifies the phase difference,the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal, andthe voltage controlled oscillator receives the phase control signal for controlling a frequency of the first clock signal; and
a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.
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Abstract
A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.
9 Citations
12 Claims
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1. A time delay apparatus for generating a plurality of phase shifted signals comprising:
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a phase locked loop generating a phase control signal, the phase locked loop comprising a voltage controlled oscillator that generates a first clock signal; a frequency divider for dividing the first clock signal; receiving means for receiving a second clock signal; and a phase comparator for comparing a phase difference between an output of the frequency divider and the second clock signal to produce the phase control signal; wherein; the phase control signal specifies the phase difference, the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal, and the voltage controlled oscillator receives the phase control signal for controlling a frequency of the first clock signal; and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A time delay apparatus for generating a plurality of phase shifted signals comprising:
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a comparator receiving at least one wave signal and generating at least one digital signal by shaping the at least one wave signal; a phase locked loop generating a phase control signal, the phase locked loop comprising a voltage controlled oscillator that generates a first clock signal; a frequency divider for dividing the first clock signal; receiving means for receiving a second clock signal; and a phase comparator for comparing a phase difference between an output of the frequency divider and the second clock signal to produce the phase control signal; wherein; the phase control signal specifies the phase difference, the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal, and the voltage controlled oscillator receives the phase control signal for controlling a frequency of the first clock signal; and a phase interpolator receiving the at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.
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Specification
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Current AssigneeAgency For Science Technology and Research
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Original AssigneeAgency For Science Technology and Research
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InventorsYin, Jee Khoi, Lim, Teck Hwee, Chia, Yan Wah Michael
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Primary Examiner(s)Donovan; Lincoln
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Assistant Examiner(s)Poos; John W
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Application NumberUS11/911,728Publication NumberTime in Patent Office1,876 DaysField of Search327/147, 327/156, 327/161, 327/242, 375/371, 331/17US Class Current327/158CPC Class CodesH01Q 3/30 varying the relative phase ...H01Q 3/38 the phase-shifters being di...H03L 7/0805 the loop being adapted to p...H03L 7/0891 the up-down pulses controll...H03L 7/18 using a frequency divider o...
