Parallel data processing apparatus

• US 7,958,332 B2
• Filed: 03/13/2009
• Issued: 06/07/2011
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Cameron, Ken, Faulds, Gordon, Stuttard, Dave, Day, Tim, O'Dea, Eamon, McConnell, Ray, Rhoades, John, Winser, Paul, David, Russell, Greer, Trey, Atkin, Phil, Williams, Dave
• Primary Examiner(s): Treat; William M
• Application Number:
  US12/404,222
• Publication Number:
  US 20090228683A1
• Time in Patent Office: 816 Days
• Field of Search: 345501-506, 345/519, 345/522, 712 10- 20, 712/22
• US Class Current: 712/16
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

Claims

1. A controller operable to control an array of processing elements, the controller comprising:

a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items;

a combining unit operable to combine the plurality of instruction streams into a serial instruction stream;

a distribution unit operable to distribute the serial instruction stream to an array of processing elements;

a plurality of instruction stream processors, one for each instruction stream, for controlling the respective instruction streams;

a semaphore controller for controlling synchronization between instruction streams, wherein each of the instruction streams includes at least one semaphore value to indicate the availability of said instruction stream, and wherein said semaphore controller is configured to set semaphore operations including a preset operation, a wait operation, and a signal operation;

an embedded processor unit configured for reading, presetting, incrementing, and decrementinq semaphore signals;

a status block for providing status information regarding each of the instruction streams; and

a scheduler connected to receive status information, and operable to determine which of the instruction streams is to be active.

2. A controller as claimed in claim 1, wherein the retrieval unit comprises a plurality of retrieval devices, each of which is assignable to one or more of the plurality of instruction streams.

3. A controller as claimed in claim 1, wherein the distribution unit is operable to distribute the serial instruction stream to one or more function controllers operable to control respective functional units.

4. A controller as claimed in claim 1, wherein the distribution unit is operable to distribute the serial instruction stream to a function controller operable to control the processing elements.

5. A controller as claimed in claim 1, wherein the distribution unit is operable to distribute the serial instruction stream to a function controller operable to control input/output functions of the array of processing elements.

6. A controller as claimed in claim 1, wherein the distribution unit is operable to distribute the serial instruction stream to a first function controller operable to control the processing elements, and wherein the distribution unit is operable to distribute the serial instruction stream to a second function controller operable to control input/output functions of the array of processing elements, the first and second function controllers operating asynchronously.

7. A controller as claimed in claim 1, wherein the distribution unit is operable to distribute selectively the serial instruction stream to either an array controller which controls data processing of the array of processing elements, or to a channel controller which controls the transfer of data to and from the processing elements.

8. A controller as claimed in claim 1, comprising a cache memory for storing retrieved instruction items.

9. A controller as claimed in claim 1, comprising a first-in-first-out buffer for storing retrieved instruction items.

10. A controller as claimed in claim 1, comprising a synchronisation controller for controlling synchronisation between instruction streams.

11. A controller as claimed in claim 1, comprising a synchronisation controller for controlling synchronisation between instruction streams and external hardware units.

12. A controller as claimed in claim 1, wherein each instruction stream is assigned a relative priority level.

13. A controller as claimed in claim 1, comprising a scheduler connected to receive status information from functional units external to the array of processing elements, and operable to schedule instruction streams using such received status information.

14. A controller as claimed in claim 1, wherein the array of processors is a SIMD (single instruction multiple data) array.

15. A controller as claimed in claim 1, wherein the distribution unit is operable to distribute selectively the serial instruction stream to either an array controller which controls data processing of the array of processing elements, or a channel controller which controls the transfer of data between external memory and internal memory units of the processing elements.

16. A controller operable to control an array of processing elements, the controller comprising:

a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items;

a combining unit operable to combine the plurality of instruction streams into a serial instruction stream;

a distribution unit operable to distribute the serial instruction stream to an array of processing elements;

an instruction stream processor for controlling a plurality of instruction streams;

a semaphore controller for controlling synchronization between instruction streams, wherein each of the instruction streams includes at least one semaphore value to indicate the availability of said instruction stream, and wherein said semaphore controller is configured to set semaphore operations including a preset operation, a wait operation, and a signal operation;

an embedded processor unit configured for reading, presetting, incrementing, and decrementinq semaphore signals;

a status block for providing status information regarding each of the instruction streams; and

a scheduling means connected to receive status information, and operable to determine which of the instruction streams is to be active.