Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof

• US 7,961,534 B2
• Filed: 09/05/2008
• Issued: 06/14/2011
• Est. Priority Date: 09/10/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hong, Suk Kyoung, Kang, Hee Bok
• Primary Examiner(s): Yoha; Connie C
• Application Number:
  US12/204,965
• Publication Number:
  US 20090067229A1
• Time in Patent Office: 1,012 Days
• Field of Search: 365/163, 365/175, 365/189.01
• US Class Current: 365/193
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2013/0052 Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.

Claims

1. A semiconductor memory device comprising:

a read/write bit line configured to supply a cell driving voltage;

a selecting unit connected to the read/write bit line and controlled by a word line;

a plurality of cells connected between the selecting unit and a source line and configured to read/write data according to the cell driving voltage; and

a plurality of switching elements connected in parallel to the plurality of cells and controlled selectively by a plurality of bit lines,

wherein a plurality of bits are simultaneously stored in the plurality of cells depending on control of the plurality of bit lines and turning-on of the selecting unit in activation of the word line.

2. The semiconductor memory device according to claim 1, wherein the selecting unit comprises a selecting switch configured to control a connection between the read/write bit line and the first cell of the plurality of cells according to the word line.

3. The semiconductor memory device according to claim 1, wherein each switching element of the plurality of switching elements comprises a MOS transistor.

4. The semiconductor memory device according to claim 1, wherein each switching element of the plurality of switching elements comprises a bipolar junction transistor.

5. The semiconductor memory device according to claim 1, wherein each switching element of the plurality of switching elements comprises a PNPN diode.

6. The semiconductor memory device according to claim 1, wherein each switching element the plurality of switching elements is connected in parallel to a single cell the plurality of cells.

7. The semiconductor memory device according to claim 1, further comprising:

a write driving unit configured to selectively supply a driving voltage to the plurality of bit lines;

a global write driving unit configured to supply the cell driving voltage to the read/write bit line; and

a source driving unit configured to supply a ground voltage or a write voltage to the source line.

8. The semiconductor memory device according to claim 1, wherein each cell of the plurality of cells comprises a phase change resistance cell, the phase change resistance cell comprising a phase change resistor.

9. The semiconductor memory device according to claim 1, wherein each cell of the plurality of cells comprises a Magnetic Tunnel Junction (MTJ) cell, the MTJ cell comprising an MTJ element.

10. The semiconductor memory device according to claim 1, wherein each cell of the plurality of cells comprises a resistance switch cell, the resistance switch cell comprising a resistive switch element.

11. The semiconductor memory device according to claim 1, wherein the read/write bit line is shared by a plurality of selecting units.

12. The semiconductor memory device according to claim 1, wherein the source line is shared by a plurality of cells connected to a bit line.