Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques
First Claim
1. A computer-implemented method of designing layouts of integrated circuits, the method comprising:
- performing a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit;
extracting parasitics of the integrated circuit based on the netlist and the layout;
performing static timing analysis on the netlist based on the layout and the parasitics, to estimate timing behavior of the netlist and to identify at least one violation by said timing behavior of a corresponding timing requirement at an endpoint of a path in the netlist;
performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said timing behavior, and said violation by;
(a) identifying a plurality of victim nets located in a fanin cone of said endpoint and identifying a group of aggressor nets, wherein each aggressor net is capacitively coupled to one of said victim nets;
(b) forming a set of candidate nets including said group of aggressor nets and said plurality of victim nets;
(c) estimating at least one change in timing behavior of each candidate net required to be made to overcome said violation; and
(d) choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c);
generating an ECO constraint on timing behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation;
automatically selecting said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and
repairing said layout by applying said ECO repair technique to generate a modified layout corrected for said violation.
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Abstract
Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.
26 Citations
34 Claims
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1. A computer-implemented method of designing layouts of integrated circuits, the method comprising:
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performing a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; extracting parasitics of the integrated circuit based on the netlist and the layout; performing static timing analysis on the netlist based on the layout and the parasitics, to estimate timing behavior of the netlist and to identify at least one violation by said timing behavior of a corresponding timing requirement at an endpoint of a path in the netlist; performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said timing behavior, and said violation by; (a) identifying a plurality of victim nets located in a fanin cone of said endpoint and identifying a group of aggressor nets, wherein each aggressor net is capacitively coupled to one of said victim nets; (b) forming a set of candidate nets including said group of aggressor nets and said plurality of victim nets; (c) estimating at least one change in timing behavior of each candidate net required to be made to overcome said violation; and (d) choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c); generating an ECO constraint on timing behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; automatically selecting said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and repairing said layout by applying said ECO repair technique to generate a modified layout corrected for said violation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer-implemented method of designing layouts of integrated circuits, the method comprising:
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performing a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; extracting parasitics of the integrated circuit based on the netlist and the layout; performing static noise analysis on the netlist based on the layout and the parasitics, to estimate noise behavior of the netlist and to identify at least one violation by said noise behavior of a corresponding noise requirement on a victim net in the netlist; performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said noise behavior, and said violation by; (a) identifying a group of aggressor nets capacitively coupled to said victim net; (b) forming a set of candidate nets including said group of aggressor nets and said victim net; (c) estimating at least one change in noise behavior of each candidate net required to be made to overcome said violation; and (d) choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c); generating an ECO constraint on noise behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; automatically selecting said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and repairing said layout by applying said ECO repair technique to generate a modified layout corrected for said violation. - View Dependent Claims (11, 12, 13)
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14. A computer-implemented method of designing layouts of integrated circuits, the method comprising:
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receiving a netlist of an integrated circuit to be fabricated; performing a place and route operation on the netlist, to produce a layout for the integrated circuit; extracting parasitics of the integrated circuit based on the netlist and the layout; performing analysis of at least one of (timing and noise) on the netlist based on the layout and the parasitics, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement; performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said behavior, and said violation; generating an ECO constraint on said behavior based on a result of said performing ECO analysis; testing on said layout each ECO repair technique in a plurality of ECO repair techniques successively, until an ECO repair technique is found to satisfy said ECO constraint; and repairing said layout by applying said ECO repair technique found to be satisfactory by said testing, to generate a modified layout corrected for said violation. - View Dependent Claims (15, 16)
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17. A non-transitory computer-readable medium storing a plurality of instructions to implement designing of layouts of integrated circuits, the plurality of instructions comprising:
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instructions to perform a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; instructions to extract parasitics of the integrated circuit based on at least one of the netlist and the layout; instructions to perform static timing analysis on the netlist based on the layout and the parasitics, to estimate timing behavior of the netlist and to identify at least one violation by said timing behavior of a corresponding timing requirement at an endpoint of a path in the netlist; instructions to perform engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said timing behavior, and said violation by execution of; (a) instructions to identify a plurality of victim nets located in a fanin cone of said endpoint and identify a group of aggressor nets, wherein each aggressor net is capacitively coupled to one of said victim nets; (b) instructions to form a set of candidate nets including said group of aggressor nets and said plurality of victim nets; (c) instructions to estimate at least one change in timing behavior of each candidate net required to be made to overcome said violation; and (d) instructions to choose a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated by execution of said (c) instructions to estimate; instructions to generate an ECO constraint on timing behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; instructions to automatically select said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and instructions to repair said layout by applying said ECO repair technique to generate a modified layout corrected for said violation. - View Dependent Claims (18, 19)
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20. A non-transitory computer-readable medium storing a plurality of instructions to implement designing of layouts of integrated circuits, the plurality of instructions comprising:
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instructions to perform a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; instructions to extract parasitics of the integrated circuit based on the netlist and the layout; instructions to perform static noise analysis on the netlist based on the layout and the parasitics, to estimate noise behavior of the netlist and to identify at least one violation by said noise behavior of a corresponding noise requirement on a victim net in the netlist; instructions to perform engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said noise behavior, and said violation by execution of; (a) instructions to identify a group of aggressor nets capacitively coupled to said victim net; (b) instructions to form a set of candidate nets including said group of aggressor nets and said victim net; (c) instructions to estimate at least one change in noise behavior of each candidate net required to be made to overcome said violation; and (d) instructions to choose a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated by execution of said (c) instructions to estimate; instructions to generate an ECO constraint on noise behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; instructions to automatically select said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and instructions to repair said layout by applying said ECO repair technique to generate a modified layout corrected for said violation. - View Dependent Claims (21, 22, 23)
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24. A non-transitory computer-readable medium storing a plurality of instructions to implement designing of layouts of integrated circuits, the plurality of instructions comprising:
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instructions to receive a netlist of an integrated circuit to be fabricated; performing a place and route operation on the netlist, to produce a layout for the integrated circuit; instructions to extract parasitics of the integrated circuit based on the netlist and the layout; instructions to perform analysis of at least one of (timing and noise) on the netlist based on the layout and the parasitics, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement; instructions to perform engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said behavior, and said violation; instructions to generate an ECO constraint on said behavior based on a result of said performing ECO analysis; instructions to test on said layout each ECO repair technique in a plurality of ECO repair techniques successively, until an ECO repair technique is found to satisfy said ECO constraint; and instructions to repair said layout by applying said ECO repair technique found to be satisfactory by said testing, to generate a modified layout corrected for said violation. - View Dependent Claims (25, 26)
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27. A non-transitory computer-readable medium storing a plurality of instructions to implement designing of layouts of integrated circuits, the plurality of instructions comprising:
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instructions to perform a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; instructions to extract parasitics of the integrated circuit based on the netlist and the layout; instructions to perform static timing analysis on the netlist based on the layout and the parasitics, to estimate timing behavior of the netlist and to identify at least one violation by said timing behavior of a corresponding timing requirement at an endpoint of a path in the netlist; instructions to perform engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said timing behavior, and said violation by execution of; (a) instructions to identify a plurality of victim nets located in a fanin cone of said endpoint and identifying a group of aggressor nets, wherein each aggressor net is capacitively coupled to one of said victim nets; (b) instructions to form a set of candidate nets including said group of aggressor nets and said plurality of victim nets; (c) instructions to estimate at least one change in timing behavior of each candidate net required to be made to overcome said violation; and (d) instructions to choose a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c); instructions to generate an ECO constraint on timing behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; instructions to automatically select said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and instructions to repair said layout by applying said ECO repair technique to generate a modified layout corrected for said violation; wherein said (c) instructions to estimate comprise instructions to compute a change in crosstalk delay in at least said victim net by using values of total resistance and total capacitance of said victim net and an aggressor net, and input capacitance of receiver cells of said victim net and said aggressor net, and resistance of said victim net'"'"'s driver cell and resistance of said aggressor net'"'"'s driver cell. - View Dependent Claims (28, 29)
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30. A non-transitory computer-readable medium storing a plurality of instructions to implement designing of layouts of integrated circuits, the plurality of instructions comprising:
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instructions to perform a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; instructions to extract parasitics of the integrated circuit based on the netlist and the layout; instructions to perform static noise analysis on the netlist based on the layout and the parasitics, to estimate noise behavior of the netlist and to identify at least one violation by said noise behavior of a corresponding noise requirement on a victim net in the netlist; instructions to perform engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said noise behavior, and said violation by execution of; (a) instructions to identify a group of aggressor nets capacitively coupled to said victim net; (b) instructions to form a set of candidate nets including said group of aggressor nets and said victim net; (c) instructions to estimate at least one change in noise behavior of each candidate net required to be made to overcome said violation; and (d) instructions to choose a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated by execution of said (c) instructions to estimate; instructions to generate an ECO constraint on noise behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; instructions to automatically select said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and instructions to repair said layout by applying said ECO repair technique to generate a modified layout corrected for said violation wherein said (c) instructions to estimate comprise instructions to compute a change in crosstalk delay in at least said victim net by using values of total resistance and total capacitance of said victim net and an aggressor net, and input capacitance of receiver cells of said victim net and said aggressor net, and resistance of said victim net'"'"'s driver cell and resistance of said aggressor net'"'"'s driver cell. - View Dependent Claims (31, 32)
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33. A non-transitory computer-readable medium storing a plurality of instructions to implement designing of layouts of integrated circuits, the plurality of instructions comprising:
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instructions to receive a netlist of an integrated circuit to be fabricated; instructions to perform a place and route operation on the netlist, to produce a layout for the integrated circuit; instructions to extract parasitics of the integrated circuit based on the netlist and the layout; instructions to perform analysis of at least one of (timing and noise) on the netlist based on the layout and the parasitics, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement; instructions to perform engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said behavior, and said violation; gene instructions to generate an ECO constraint on said behavior based on a result of said performing ECO analysis; instructions to test on said layout each ECO repair technique in a plurality of ECO repair techniques successively, until an ECO repair technique is found to satisfy said ECO constraint; and instructions to repair said layout by applying said ECO repair technique found to be satisfactory by execution of said instruction to test, to generate a modified layout corrected for said violation; wherein said instruction to perform ECO analysis comprise instructions to estimate at least one change in behavior of a first net in the netlist to overcome said violation; and wherein said instructions to estimate comprise instructions to compute a change in crosstalk delay in said first net by using values of total resistance and total capacitance of said first net and a second net in said netlist, and the input capacitance of receiver cells of said first net and said second net, and resistance of said first net'"'"'s driver cell and resistance of said second net'"'"'s driver cell. - View Dependent Claims (34)
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Specification