Flash memory device with multi-level cells and method of writing data therein
First Claim
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1. A method of writing data in a flash memory system including a single-level cell (SLC) block and a multi-level cell (MLC) block, the flash memory system forming an address mapping pattern according to a log block mapping scheme, the method comprising:
- determining a writing pattern of data to be written in a log block; and
selectively allocating one of the SLC block and the MLC block to the log block in accordance with the writing pattern of the data,wherein the writing pattern includes a sequential-writing pattern in which data are sequentially written into the log block in a unit of a page, and a random-writing pattern in which data are written into the log block out of sequence in a unit of a page, andwherein the MLC block is allocated to the log block when the writing pattern of the data is the sequential-writing pattern, and the SLC block is allocated to the log block when the writing pattern of the data is the random-writing pattern.
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Abstract
In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.
26 Citations
23 Claims
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1. A method of writing data in a flash memory system including a single-level cell (SLC) block and a multi-level cell (MLC) block, the flash memory system forming an address mapping pattern according to a log block mapping scheme, the method comprising:
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determining a writing pattern of data to be written in a log block; and selectively allocating one of the SLC block and the MLC block to the log block in accordance with the writing pattern of the data, wherein the writing pattern includes a sequential-writing pattern in which data are sequentially written into the log block in a unit of a page, and a random-writing pattern in which data are written into the log block out of sequence in a unit of a page, and wherein the MLC block is allocated to the log block when the writing pattern of the data is the sequential-writing pattern, and the SLC block is allocated to the log block when the writing pattern of the data is the random-writing pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of writing data in multi-level cell (MLC) flash memory system including a first MLC block and a second MLC block, the flash memory system forming an address mapping pattern according to a log block mapping scheme, the method comprising:
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determining a writing pattern of data to be written in the MLC flash memory; selectively allocating one of the first MLC block and the second MLC block to a log block for a write buffer hi accordance with the writing pattern of the data, wherein the writing pattern includes a sequential-writing pattern in which data are sequentially written into the log block in a unit of a page., and a random-writing pattern by which data are written into the log block out of sequence in a unit of a page, wherein the first MLC block is an MLC block with fast pages selected as available storage fields and the second MLC block is an MLC block with fast and slow pages selected as available storage fields, and wherein a slow page among the slow pages of the second MLC block is allocated to the log block when the writing pattern of the data is the sequential-writing pattern, and a fast page among the fast pages of the first and second MLC blocks is allocated to the log block when the writing pattern of the data is the random-writing pattern. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of mapping addresses in a flash memory system, the flash memory system forming an address mapping pattern in accordance with a log block mapping scheme, the method comprising:
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including a plurality of single-level cell (SLC) blocks in a log block; and using an multi-level cell (MLC) block for a data block corresponding to the log block, wherein an SLC block is allocated to the log block when page data to be written into the flash memory is in a random-writing pattern, and wherein the MLC block is allocated to the log block when the page data to be written into the flash memory is in a sequential-writing pattern. - View Dependent Claims (17)
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18. A memory system which forms an address mapping pattern in accordance with a log block mapping scheme, comprising:
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a flash memory device including pluralities of single-level cell (SLC) and multi-level cell (MLC) blocks as storage fields; and a controller which detects a writing pattern of externally supplied data and which selects a part of the SLC blocks or one of the plural MLC blocks as a log block in accordance with the detected writing pattern, wherein the writing pattern includes a sequential-writing pattern in which data are sequentially written into the log block in a unit of a page, and a random-writting pattern in which data are written into the log block out of sequence in a unit of a page, and wherein the controller allocates one of the plural MLC blocks to the log block when the writing pattern of the data is detected as the sequential-writing pattern, and allocates one of the plural SLC blocks to the log block when the writing pattern of the data is detected as the random-writing pattern. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification