External memory controller node
First Claim
Patent Images
1. A computing machine comprising:
- a memory;
a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory; and
a memory controller configured to place the requests for memory accesses in a queue and allow accesses by the heterogeneous computational nodes to the memory in an order established by the queue.
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Accused Products
Abstract
A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
408 Citations
43 Claims
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1. A computing machine comprising:
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a memory; a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory; and a memory controller configured to place the requests for memory accesses in a queue and allow accesses by the heterogeneous computational nodes to the memory in an order established by the queue. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computing machine embodied in an integrated circuit and in communication with an external memory device, the computing machine comprising:
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a plurality of heterogeneous computational nodes configured to make requests for data transfer to the external memory device; and a controller configured to place the requests for data transfer in a queue and allow accesses by the heterogeneous computational nodes to the external memory device in an order established by the queue. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An adaptive computing machine comprising:
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a memory; a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory; a programmable interconnection network providing programmable interconnections among the heterogeneous computational nodes; and a memory controller including ports that have parameters, the memory controller configured to generate memory locations for the requests based on the parameters and to allow accesses by the heterogeneous computational nodes to the memory at the memory locations in response to the requests and to place the memory requests in a queue and allow accesses by the heterogeneous computational nodes to the memory in an order established by the queue. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. An adaptive computing machine embodied in an integrated circuit and in communication with an external memory device, the adaptive computing machine comprising:
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a plurality of heterogeneous computational nodes configured to make requests for data transfer to the external memory device; a programmable interconnection network to provide programmable interconnections among the heterogeneous computational nodes; and a controller configured to place the requests for data transfer in a queue and allow accesses by the heterogeneous computational nodes to the external memory device in an order established by the queue. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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Specification